[AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks

In some cases the lack of --- or ... confused update_mir_test_checks.py
into not adding any checks for a function.

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir

@@ -370,3 +370,4 @@ body:             |
     %assert_sext:_(s32) = G_ASSERT_SEXT %copy, 8
     %sext_inreg:_(s32) = G_SEXT_INREG %assert_sext, 7
     $vgpr0 = COPY %sext_inreg
+...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir

@@ -50,6 +50,7 @@ body: |
     %17:sgpr(s512) = G_INSERT %16:sgpr, %1:sgpr(s32), 480
     $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %17:sgpr(s512)
     SI_RETURN_TO_EPILOG $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
+...
 
 ---
 
@@ -60,6 +61,11 @@ regBankSelected: true
 body: |
   bb.0:
     liveins:  $vgpr0_vgpr1, $vgpr2
+    ; CHECK-LABEL: name: insert_v_s64_v_s32_0
+    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:vreg_64 = INSERT_SUBREG [[COPY]], [[COPY1]], %subreg.sub0
+    ; CHECK: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
     %0:vgpr(s64) = COPY $vgpr0_vgpr1
     %1:vgpr(s32) = COPY $vgpr2
     %2:vgpr(s64) = G_INSERT %0, %1, 0
@@ -598,3 +604,4 @@ body: |
     %1:sgpr(<2 x s16>) = COPY $sgpr2
     %2:sgpr(<4 x s16>) = G_INSERT %0, %1, 32
     S_ENDPGM 0, implicit %2
+...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir

@@ -263,11 +263,26 @@ body: |
     G_STORE %1, %0 :: (store 1, addrspace 1)
 ...
 
+---
 name: test_store_global_i1
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1, $vgpr2
 
+    ; SI-LABEL: name: test_store_global_i1
+    ; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+    ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+    ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+    ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+    ; SI: G_STORE [[AND]](s32), [[COPY]](p1) :: (store 1, addrspace 1)
+    ; VI-LABEL: name: test_store_global_i1
+    ; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+    ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
+    ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
+    ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+    ; VI: G_STORE [[AND]](s32), [[COPY]](p1) :: (store 1, addrspace 1)
     %0:_(p1) = COPY $vgpr0_vgpr1
     %1:_(s32) = COPY $vgpr2
     %2:_(s1) = G_TRUNC %1

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir

@@ -1028,6 +1028,7 @@ body: |
     S_NOP 0, implicit %2
 ...
 
+---
 name: test_unmerge_s8_v4s8
 body: |
   bb.0:

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir

@@ -170,6 +170,7 @@ body: |
     %1:_(<16 x s32>) = G_LOAD %0 :: (load 64 from %ir.global.not.uniform.v16i32)
 ...
 
+---
 name: load_global_v8i64_non_uniform
 legalized: true
 

llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir

@@ -1106,5 +1106,3 @@ body:             |
     renamable $agpr4_agpr5_agpr6_agpr7 = COPY renamable killed $agpr0_agpr1_agpr2_agpr3, implicit $exec
     S_ENDPGM 0, implicit $agpr4_agpr5_agpr6_agpr7
 ...
-
----

llvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir

@@ -49,3 +49,4 @@ body:             |
     %6:sreg_64 = V_CMP_EQ_U32_e64 killed %4, killed %5, implicit $exec
     %1:vreg_1 = COPY %6
     S_BRANCH %bb.1
+...

llvm/test/CodeGen/AMDGPU/pei-build-spill-partial-agpr.mir

@@ -43,6 +43,7 @@
   attributes #2 = { nounwind "amdgpu-num-vgpr"="3" }
   attributes #3 = { nounwind "amdgpu-num-vgpr"="4" }
   attributes #4 = { nounwind "amdgpu-num-vgpr"="5" }
+...
 
 ---
 name:            test_spill_v2_partial_agpr

llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir

@@ -189,10 +189,18 @@ body:             |
   S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
 ...
 
+---
 name:            different_imm_index
 body:             |
   bb.0:
 
+    ; GCN-LABEL: name: different_imm_index
+    ; GCN: S_SET_GPR_IDX_ON 1, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode
+    ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0
+    ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
+    ; GCN: S_SET_GPR_IDX_ON 2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode
+    ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0
+    ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
   S_SET_GPR_IDX_ON 1, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode
   $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0
   S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode