Simulating in Icarus

tenyr currently requires a very new version of Icarus Verilog to run - version 0.10.0, which can be built from source, but is not released as a package at the time of writing.

To build the Verilog HDL sources into an executable Icarus Verilog script, type make -C hw/icarus from the top-level tenyr source directory.

$ make -C hw/icarus
make: Entering directory '.../tenyr/hw/icarus'
[ IVERILOG ] tenyr
make: Leaving directory '.../tenyr/hw/icarus'

A plugin module using VPI is also required. For this, just type make vpi at the top level.

kulp@kagi tenyr(brooke) $ make vpi
mkdir -p .../tenyr//build/x86_64-linux-gnu
make TOOLDIR=.../tenyr//build/x86_64-linux-gnu BUILDDIR=. -C .../tenyr//build/x86_64-linux-gnu -f .../tenyr/Makefile TOP=.../tenyr/ vpi
[ DYCC ] callbacks.c
[ DYCC ] vpiserial.c
[ DYCC ] load.c
[ DYCC ] sim.c
[ DYCC ] asm.c
[ DYCC ] obj.c
[ DYCC ] common.c
[ DYCC ] param.c
[ DYCC ] vpidevices.c
[ VPI ] vpidevices.vpi
rm vpidevices,dy.o

This will create a vpidevices.vpi file in your build directory (which can be shown with make showbuilddir).

Now you are ready to run a tenyr code under the simulated Verilog machine. While it is possible to set up the command line for this manually, an easier way is to use the run_% target in hw/icarus/Makefile. This will search several directories for ways to build a .texe file with the appropriate name (e.g. if you type make run_mytest the Makefile will search for rules to build mytest.texe). If you're testing a new code, try putting it either in ex/ or in hw/icarus.

Here we use V=1 on the command line to show the commands being executed. The .texe file is automatically built if it does not exist, and then vvp is run with the correct arguments to load that .texe file into the simulator. Here is a test of the shortest legal terminating program :

 $ cd hw/icarus
 $ echo illegal > tiniest.tas
 $ make run_tiniest V=1
mkdir -p .
.../tenyr/build/x86_64-linux-gnu/tas -otiniest.to tiniest.tas
.../tenyr/build/x86_64-linux-gnu/tld -otiniest.texe tiniest.to
vvp -n -M.../tenyr/build/x86_64-linux-gnu tenyr +LOAD=tiniest.texe +PERIODS=32 +LOGFILE=Top.vcd
WARNING: ../verilog/ram.v:27: $readmemh: Standard inconsistency, following 1364-2005.
ERROR: ../verilog/ram.v:27: $readmemh: Unable to open default.memh for reading.
VCD info: dumpfile Top.vcd opened for output.
rm tiniest.texe tiniest.tas tiniest.to

Now the file Top.vcd contains a Value Change Dump file that can be opened with GTKWave or similar.

By default only 32 periods of the clock are simulated. This is not enough for any program of reasonable length, so you will probably want to set PERIODS=1000 or some other value on the make command line :

$ make run_tiniest PERIODS=2000
[ TAS ] tiniest.tas
[ TLD ] tiniest.texe
WARNING: ../verilog/ram.v:27: $readmemh: Standard inconsistency, following 1364-2005.
ERROR: ../verilog/ram.v:27: $readmemh: Unable to open default.memh for reading.
VCD info: dumpfile Top.vcd opened for output.
rm tiniest.texe tiniest.tas tiniest.to

Once you have the .vcd file loaded in GTKWave, you can select signals to view. You can also use the Translate Filter File and Translate Filter Process features with the files in scripts/gtkwave to translate signals automatically (e.g., to show the decoding of an instruction).