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This is the firmware, written in Verilog, for the Xilinx FPGA on the FPGA1394 board, which is Spartan 6 for FPGA1394 V1, V2 and Zynq 7000 for FPGA1394 V3. All versions can be compiled with the Xilinx ISE software, and the V3 firmware can be compiled with Xilinx Vivado.

See http://jhu-cisst.github.io/mechatronics/ for board details.

See https://github.com/jhu-cisst/mechatronics-embedded for the embedded software that runs on the Zynq ARM processor in FPGA1394 V3.

See https://github.com/jhu-cisst/mechatronics-software/wiki for information about the C++ library (Amp1394) that provides the PC interface to the firmware. In particular, see the Interface Specification (packet formats).

This wiki is also a git repository and can be cloned as follows:

git clone https://github.com/jhu-cisst/mechatronics-firmware.wiki.git

This is the easiest way to add images, which are stored in the assets directory. Note that the source files (e.g., Powerpoint) for some images are included.

List of branches

• main: main branch
• devel: development branch
• feature-digital-control: digital control on the FPGA, for QLA boards modified as described here

Files

• Verilog: verilog for all modules
• ipcore_dir: generated ip cores for any FPGA version
• ipcorev3_dir: generated ip cores for FPGA V3
• Simulation: test bed files + old .do files (not actively maintained)
• Chipscope: chipscope project for debug purpose (not actively maintained)
  • some data bus and names

Documentation

How-to and Release Notes

• How to install Xilinx ISE on Linux
• Build instructions
• FPGA Debug: ChipScope
• How to program the FPGA controller board
• FPGA firmware releases

Firmware Documentation

• FPGA Design
• Timing Diagrams
• FPGA Module Block Diagram
• FPGA Broadcast Firmware
• Ethernet Interface Design
• Ethernet Packet Format
• Ethernet Switch Design (FPGA V3)

Reference

• List of Xilinx file suffixes:
  • http://tinyurl.com/nbqhuna