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Bump to llvm/llvm-project@3f1486f #19683

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merged 11 commits into from
Jan 17, 2025
+45 −24
Merged

Bump to llvm/llvm-project@3f1486f #19683

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bcf9d09
Bump to https://github.com/llvm/llvm-project/commit/3f1486f08e0dd6413…
MaheshRavishankar Jan 13, 2025
3f28c51
Update reverts
MaheshRavishankar Jan 13, 2025
870f29c
Revert https://github.com/llvm/llvm-project/commit/a0f5bbcfb71a28cd3e…
MaheshRavishankar Jan 13, 2025
b8e1824
Update Torch-mlir for change in Conv2D op definition.
MaheshRavishankar Jan 13, 2025
0d57e70
Register `ValuesBoundsOpInterfaceExternalModels` for `gpu` ops.
MaheshRavishankar Jan 14, 2025
1d48f45
Update tosa.pad unit tests to follow new op semantics.
ScottTodd Jan 16, 2025
22c015e
Add GPU dialect as a dependency to external dialect registration to f…
krzysz00 Jan 16, 2025
14e195b
Revert LLVM PR to fix ASan issues
ScottTodd Jan 16, 2025
a745991
Mark TFLite (TOSA) model tests XFAIL and log a compatibility warning.
ScottTodd Jan 16, 2025
fa9267d
Update spirv tests for changes to sub-byte lowering
krzysz00 Jan 17, 2025
208ff2c
Add dependency on GPU dialect to one more spot
krzysz00 Jan 17, 2025
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1 change: 1 addition & 0 deletions compiler/src/iree/compiler/Codegen/Interfaces/BUILD.bazel
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Expand Up @@ -62,6 +62,7 @@ iree_compiler_cc_library(
"@llvm-project//mlir:AMDGPUDialect",
"@llvm-project//mlir:ArithValueBoundsOpInterfaceImpl",
"@llvm-project//mlir:BufferizationTransformOps",
"@llvm-project//mlir:GPUDialect",
"@llvm-project//mlir:GPUTransformOps",
"@llvm-project//mlir:LinalgDialect",
"@llvm-project//mlir:LinalgTransformOps",
Expand Down
1 change: 1 addition & 0 deletions compiler/src/iree/compiler/Codegen/Interfaces/CMakeLists.txt
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Expand Up @@ -28,6 +28,7 @@ iree_cc_library(
MLIRAffineTransformOps
MLIRArithValueBoundsOpInterfaceImpl
MLIRBufferizationTransformOps
MLIRGPUDialect
MLIRGPUTransformOps
MLIRIR
MLIRLinalgDialect
Expand Down
2 changes: 2 additions & 0 deletions compiler/src/iree/compiler/Codegen/Interfaces/Interfaces.cpp
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Expand Up @@ -23,6 +23,7 @@
#include "mlir/Dialect/Affine/TransformOps/AffineTransformOps.h"
#include "mlir/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.h"
#include "mlir/Dialect/Bufferization/TransformOps/BufferizationTransformOps.h"
#include "mlir/Dialect/GPU/IR/ValueBoundsOpInterfaceImpl.h"
#include "mlir/Dialect/GPU/TransformOps/GPUTransformOps.h"
#include "mlir/Dialect/Linalg/IR/ValueBoundsOpInterfaceImpl.h"
#include "mlir/Dialect/Linalg/TransformOps/DialectExtension.h"
Expand Down Expand Up @@ -64,6 +65,7 @@ void registerCodegenInterfaces(DialectRegistry &registry) {
arith::registerValueBoundsOpInterfaceExternalModels(registry);
bufferization::registerTransformDialectExtension(registry);
gpu::registerTransformDialectExtension(registry);
gpu::registerValueBoundsOpInterfaceExternalModels(registry);
linalg::registerTransformDialectExtension(registry);
linalg::registerValueBoundsOpInterfaceExternalModels(registry);
linalg::registerSubsetOpInterfaceExternalModels(registry);
Expand Down
19 changes: 9 additions & 10 deletions compiler/src/iree/compiler/Codegen/SPIRV/test/pipeline_matvec.mlir
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Expand Up @@ -76,18 +76,18 @@ hal.executable @i4_dequant_unit_matmul_f16 {

// CHECK-DAG: %[[CSTVEC4XI32_255:.+]] = spirv.Constant dense<255> : vector<4xi32>
// CHECK-DAG: %[[CSTVEC4XI32_0:.+]] = spirv.Constant dense<0> : vector<4xi32>
// CHECK-DAG: %[[CSTVEC2XI32_4:.+]] = spirv.Constant dense<4> : vector<2xi32>
// CHECK-DAG: %[[CSTVEC2XI32_15:.+]] = spirv.Constant dense<15> : vector<2xi32>
// CHECK-DAG: %[[CSTVEC4XI32_0_4:.+]] = spirv.Constant dense<[0, 4, 0, 4]> : vector<4xi32>
// CHECK-DAG: %[[CSTVEC4XI32_15__16:.+]] = spirv.Constant dense<[15, -16, 15, -16]> : vector<4xi32>

// CHECK: spirv.mlir.loop

// Load the quantized weight and get 8xi4 out of it.
// CHECK: %[[LOAD:.+]] = spirv.Load "StorageBuffer" %{{.+}} : vector<4xi32>
// CHECK: %[[SHUF01:.+]] = spirv.VectorShuffle [0 : i32, 1 : i32] %[[LOAD]], %[[LOAD]] : vector<4xi32>, vector<4xi32> -> vector<2xi32>
// CHECK: %[[LOW4:.+]] = spirv.BitwiseAnd %[[SHUF01]], %[[CSTVEC2XI32_15]] : vector<2xi32>
// CHECK: %[[HIGH4:.+]] = spirv.ShiftRightLogical %[[SHUF01]], %[[CSTVEC2XI32_4]] : vector<2xi32>, vector<2xi32>
// CHECK: %[[LOW4HIGH4:.+]] = spirv.VectorShuffle [0 : i32, 2 : i32, 1 : i32, 3 : i32] %[[LOW4]], %[[HIGH4]] : vector<2xi32>, {{.*}} -> vector<4xi32>
// CHECK: %[[LOW4HIGH4_ZEROUPPER:.+]] = spirv.BitwiseAnd %[[LOW4HIGH4]], %[[CSTVEC4XI32_255]] : vector<4xi32>
// CHECK: %[[SHUF0011:.+]] = spirv.VectorShuffle [0 : i32, 0 : i32, 1 : i32, 1 : i32] %[[SHUF01]], %[[SHUF01]] : vector<2xi32>, vector<2xi32> -> vector<4xi32>
// CHECK: %[[MASKED:.+]] = spirv.BitwiseAnd %[[SHUF0011]], %[[CSTVEC4XI32_15__16]] : vector<4xi32>
// CHECK: %[[SHIFTED:.+]] = spirv.ShiftRightLogical %[[MASKED]], %[[CSTVEC4XI32_0_4]] : vector<4xi32>, vector<4xi32>
// CHECK: %[[LOW4HIGH4_ZEROUPPER:.+]] = spirv.BitwiseAnd %[[SHIFTED]], %[[CSTVEC4XI32_255]] : vector<4xi32>

// CHECK: %[[SHUF23:.+]] = spirv.VectorShuffle [2 : i32, 3 : i32] %[[LOAD:.+]], %[[LOAD:.+]] : vector<4xi32>, vector<4xi32> -> vector<2xi32>

Expand Down Expand Up @@ -186,8 +186,8 @@ hal.executable @i4_dequant_matvec_f16_subgroup_64 {
// CHECK-DAG: %[[C0:.+]] = spirv.Constant 0 : i32
// CHECK-DAG: %[[CSTVEC4XF16_1:.+]] = spirv.Constant dense<1.000000e+00> : vector<4xf16>
// CHECK-DAG: %[[CSTVEC4XI32_255:.+]] = spirv.Constant dense<255> : vector<4xi32>
// CHECK-DAG: %[[CSTVEC2XI32_4:.+]] = spirv.Constant dense<4> : vector<2xi32>
// CHECK-DAG: %[[CSTVEC2XI32_15:.+]] = spirv.Constant dense<15> : vector<2xi32>
// CHECK-DAG: %[[CSTVEC2XI32_1:.+]] = spirv.Constant dense<[0, 4, 0, 4]> : vector<4xi32>
// CHECK-DAG: %[[CSTVEC2XI32_2:.+]] = spirv.Constant dense<[15, -16, 15, -16]> : vector<4xi32>

// CHECK: %[[WIDX:.+]] = spirv.CompositeExtract %{{.*}}[0 : i32] : vector<3xi32>
// CHECK: %[[PCPTR:.+]] = spirv.AccessChain %{{.*}}[{{.*}}, %[[C0]]] : !spirv.ptr<!spirv.struct<(!spirv.array<5 x i32, stride=4> [0])>, PushConstant>, i32, i32
Expand All @@ -209,8 +209,7 @@ hal.executable @i4_dequant_matvec_f16_subgroup_64 {
// CHECK: %[[ACCESS:.+]] = spirv.AccessChain %[[RADDR]][{{.*}}, %[[OFFSET]]] : !spirv.ptr<!spirv.struct<(!spirv.rtarray<i32, stride=4> [0])>, StorageBuffer>, i32, i32
// CHECK: spirv.Load "StorageBuffer" %[[ACCESS]] : i32

// CHECK: spirv.ShiftRightLogical %{{.*}}, %[[CSTVEC2XI32_4]] : vector<2xi32>, vector<2xi32>
// CHECK: spirv.VectorShuffle [0 : i32, 2 : i32, 1 : i32, 3 : i32] %{{.*}} : vector<2xi32>, vector<2xi32> -> vector<4xi32>
// CHECK: spirv.ShiftRightLogical %{{.*}}, %[[CSTVEC2XI32_1]] : vector<4xi32>, vector<4xi32>
// CHECK: spirv.BitwiseAnd %{{.*}}, %[[CSTVEC4XI32_255]] : vector<4xi32>

// CHECK: spirv.ConvertUToF %{{.+}} : vector<4xi32> to vector<4xf16>
Expand Down
12 changes: 6 additions & 6 deletions compiler/src/iree/compiler/Codegen/SPIRV/test/pipeline_sub_byte_dequant.mlir
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Expand Up @@ -44,13 +44,13 @@ hal.executable @i4_dequant {

// CHECK-LABEL: spirv.func @i4_dequant()

// CHECK: spirv.VectorShuffle [0 : i32, 1 : i32] {{.*}} : vector<4xi32>, vector<4xi32> -> vector<2xi32>
// CHECK: spirv.BitwiseAnd
// CHECK: spirv.ShiftRightLogical
// CHECK: spirv.VectorShuffle [0 : i32, 2 : i32, 1 : i32, 3 : i32]
// CHECK: spirv.BitwiseAnd
// CHECK: %[[BYTE1:.+]] = spirv.VectorShuffle [0 : i32, 1 : i32] {{.*}} : vector<4xi32>, vector<4xi32> -> vector<2xi32>
// CHECK: %[[COPIED:.+]] = spirv.VectorShuffle [0 : i32, 0 : i32, 1 : i32, 1 : i32] %[[BYTE1]], %[[BYTE1]] : vector<2xi32>, vector<2xi32> -> vector<4xi32>
// CHECK: %[[MASKED:.+]] = spirv.BitwiseAnd %[[COPIED]]
// CHECK: %[[SHIFTED:.+]] = spirv.ShiftRightLogical %[[MASKED]]
// CHECK: %[[ZEROUPPER:.+]] = spirv.BitwiseAnd %[[SHIFTED]]
// CHECK: spirv.VectorShuffle [2 : i32, 3 : i32] {{.*}} : vector<4xi32>, vector<4xi32> -> vector<2xi32>
// CHECK-COUNT-3: spirv.VectorShuffle [0 : i32, 2 : i32, 1 : i32, 3 : i32]
// CHECK-COUNT-3: spirv.VectorShuffle [0 : i32, 0 : i32, 1 : i32, 1 : i32]

// CHECK-COUNT-4: spirv.ConvertUToF {{.+}} : vector<4xi32> to vector<4xf32>
// CHECK-COUNT-4: spirv.FSub
Expand Down
1 change: 1 addition & 0 deletions compiler/src/iree/compiler/ExternalInterfaces/BUILD.bazel
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Expand Up @@ -37,6 +37,7 @@ iree_compiler_cc_library(
"//compiler/src/iree/compiler/Dialect/Stream/IR",
"//compiler/src/iree/compiler/Dialect/Util/IR",
"@llvm-project//mlir:ArithDialect",
"@llvm-project//mlir:GPUDialect",
"@llvm-project//mlir:IR",
"@llvm-project//mlir:LinalgDialect",
"@llvm-project//mlir:LinalgOpsIncGen",
Expand Down
1 change: 1 addition & 0 deletions compiler/src/iree/compiler/ExternalInterfaces/CMakeLists.txt
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Expand Up @@ -27,6 +27,7 @@ iree_cc_library(
"UtilExternalModels.cpp"
DEPS
MLIRArithDialect
MLIRGPUDialect
MLIRIR
MLIRLinalgDialect
MLIRLinalgOpsIncGenLib
Expand Down
13 changes: 13 additions & 0 deletions ...flow/python_projects/iree_tflite/iree/tools/tflite/scripts/iree_import_tflite/__main__.py
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Expand Up @@ -51,6 +51,19 @@ def main():
if args.output_format != "mlir-bytecode":
logging.warning("output-format option is deprecated, emitting MLIR bytecode")

# Log compatibility warnings for some known issues.
try:
from packaging import version
from tensorflow import __version__ as tf_version

# https://discourse.llvm.org/t/rfc-tosa-dialect-increment-to-v1-0/83708
if version.parse(tf_version) <= version.parse("2.18.0"):
logging.warning(
f"Found tensorflow version {tf_version}. Versions of tensorflow<=2.18.0 have known compatibility issues with TOSA v1.0. Consider using a newer tensorflow version or iree-base-compiler<=3.1.0"
)
except:
pass

tflite_to_tosa(
flatbuffer=args.flatbuffer,
bytecode=args.output_path,
Expand Down
1 change: 1 addition & 0 deletions integrations/tensorflow/test/iree_tfl_tests/gpt2.run
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@@ -1 +1,2 @@
# RUN: %PYTHON -m iree_tfl_tests.gpt2_test --artifacts_dir=%t
# XFAIL: *
1 change: 1 addition & 0 deletions integrations/tensorflow/test/iree_tfl_tests/person_detect.run
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@@ -1 +1,2 @@
# RUN: %PYTHON -m iree_tfl_tests.person_detect_test --artifacts_dir=%t
# XFAIL: *
1 change: 1 addition & 0 deletions integrations/tensorflow/test/iree_tfl_tests/vmvx_person_detect.run
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@@ -1,2 +1,3 @@
# REQUIRES: vmvx
# RUN: %PYTHON -m iree_tfl_tests.person_detect_test --target_backend=vmvx --artifacts_dir=%t
# XFAIL: *
12 changes: 6 additions & 6 deletions tests/e2e/tosa_ops/pad.mlir
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@@ -1,23 +1,23 @@
func.func @pad_1D_test() {
%0 = util.unfoldable_constant dense<42> : tensor<2xi32>
%1 = "tosa.const"() { value = dense<[[3, 2]]> : tensor<1x2xi32> } : () -> (tensor<1x2xi32>)
%result = tosa.pad %0, %1 : (tensor<2xi32>, tensor<1x2xi32>) -> (tensor<7xi32>)
%1 = "tosa.const"() { value = dense<[3, 2]> : tensor<2xi32> } : () -> (tensor<2xi32>)
%result = tosa.pad %0, %1 : (tensor<2xi32>, tensor<2xi32>) -> (tensor<7xi32>)
check.expect_eq_const(%result, dense<[0, 0, 0, 42, 42, 0, 0]> : tensor<7xi32>) : tensor<7xi32>
return
}

func.func @pad_2D_test() {
%0 = util.unfoldable_constant dense<42> : tensor<2x2xi32>
%1 = "tosa.const"() { value = dense<[[1, 1], [1, 1]]> : tensor<2x2xi32> } : () -> (tensor<2x2xi32>)
%result = tosa.pad %0, %1 : (tensor<2x2xi32>, tensor<2x2xi32>) -> (tensor<4x4xi32>)
%1 = "tosa.const"() { value = dense<[1, 1, 1, 1]> : tensor<4xi32> } : () -> (tensor<4xi32>)
%result = tosa.pad %0, %1 : (tensor<2x2xi32>, tensor<4xi32>) -> (tensor<4x4xi32>)
check.expect_eq_const(%result, dense<[[0, 0, 0, 0], [0, 42, 42, 0], [0, 42, 42, 0], [0, 0, 0, 0]]> : tensor<4x4xi32>) : tensor<4x4xi32>
return
}

func.func @pad_3D_test() {
%0 = util.unfoldable_constant dense<42> : tensor<1x1x2xi32>
%1 = "tosa.const"() { value = dense<[[0, 1], [1, 0], [0, 0]]> : tensor<3x2xi32> } : () -> (tensor<3x2xi32>)
%result = tosa.pad %0, %1 : (tensor<1x1x2xi32>, tensor<3x2xi32>) -> (tensor<2x2x2xi32>)
%1 = "tosa.const"() { value = dense<[0, 1, 1, 0, 0, 0]> : tensor<6xi32> } : () -> (tensor<6xi32>)
%result = tosa.pad %0, %1 : (tensor<1x1x2xi32>, tensor<6xi32>) -> (tensor<2x2x2xi32>)
check.expect_eq_const(%result, dense<[[[0, 0], [42, 42]], [[0, 0], [0, 0]]]> : tensor<2x2x2xi32>) : tensor<2x2x2xi32>
return
}
2 changes: 1 addition & 1 deletion third_party/llvm-project
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Submodule llvm-project updated 2088 files
2 changes: 1 addition & 1 deletion third_party/torch-mlir
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Submodule torch-mlir updated 1 files
+4 −2 lib/Conversion/TorchToTosa/TorchToTosa.cpp
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