Match flags between different sdxl tests

experimental/benchmarks/sdxl/benchmark_sdxl_rocm.py

@@ -60,12 +60,21 @@ def run_sdxl_rocm_benchmark(rocm_chip):
         f"{benchmark_dir}/sdxl_pipeline_bench_f16.mlir",
         "--iree-hal-target-backends=rocm",
         f"--iree-hip-target={rocm_chip}",
-        "--iree-global-opt-propagate-transposes=true",
         "--iree-codegen-llvmgpu-use-vector-distribution",
         "--iree-codegen-gpu-native-math-precision=true",
-        "--iree-hip-waves-per-eu=2",
         "--iree-opt-outer-dim-concat=true",
+        "--iree-opt-const-eval=false",
+        "--iree-opt-strip-assertions=true",
+        "--iree-global-opt-propagate-transposes=true",
+        "--iree-opt-outer-dim-concat=true",
+        "--iree-hip-waves-per-eu=2",
         "--iree-llvmgpu-enable-prefetch",
+        "--iree-dispatch-creation-enable-aggressive-fusion",
+        "--iree-dispatch-creation-enable-fuse-horizontal-contractions=true",
+        "--iree-opt-aggressively-propagate-transposes=true",
+        "--iree-codegen-llvmgpu-use-vector-distribution=true",
+        "--iree-execution-model=async-external",
+        "--iree-preprocessing-pass-pipeline=builtin.module(iree-preprocessing-transpose-convolution-pipeline,iree-preprocessing-pad-to-intrinsics{pad-target-type=conv})",
         "-o",
         f"{benchmark_dir}/sdxl_full_pipeline_fp16_rocm.vmfb",
     ]