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[TKW] Enable each MMA to have it's own intrinsic #287

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merged 4 commits into from
Nov 22, 2024
Merged

[TKW] Enable each MMA to have it's own intrinsic #287

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a03e7ea
[TKW] Enable each MMA to have it's own intrinsic
raikonenfnu Nov 15, 2024
28babc8
Add attention test + fix chain gemm test to support large size
raikonenfnu Nov 21, 2024
98333f9
fix lit since we introduce optional variable
raikonenfnu Nov 21, 2024
985ee29
fix nit
raikonenfnu Nov 22, 2024
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1 change: 1 addition & 0 deletions iree/turbine/kernel/ops/wave_ops.py
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Original file line number Diff line number Diff line change
Expand Up @@ -865,6 +865,7 @@ class MMA(CustomOp):
lhs: fx.Node
rhs: fx.Node
acc: fx.Node
mma_type: Optional["MMAType"] = None

@property
def indexing_dims(self) -> list[IndexSymbol]:
Expand Down
4 changes: 2 additions & 2 deletions iree/turbine/kernel/wave/codegen.py
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Expand Up @@ -888,7 +888,7 @@ def emit_mfma(
@handle_op(mma)
def handle_mma(emitter: WaveEmitter, node: fx.Node):
try:
lhs, rhs, acc = node.args
lhs, rhs, acc, mma_type = node.args
acc = cast_vector(emitter, acc)
values = [cast_vector(emitter, val) for val in [lhs, rhs]]
except ValueError as e:
Expand All @@ -904,7 +904,7 @@ def handle_mma(emitter: WaveEmitter, node: fx.Node):
if not hardware_constraints:
raise CodegenError("No hardware constraints found.")

m, n, k = hardware_constraints[0].mma_matrix_shapes
m, n, k = hardware_constraints[0].mma_matrix_shapes(mma_type)
result = emit_mfma(m, n, k, vector_type, acc, values)
emitter.bind_node_proxy(node, IRProxyValue(result))

Expand Down
16 changes: 10 additions & 6 deletions iree/turbine/kernel/wave/constraints.py
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Expand Up @@ -121,10 +121,11 @@ def get_thread_id_from_workgroup_dim(self, workgroup_dim: int) -> IndexSymbol:
case _:
raise ValueError("Invalid workgroup dimension. Expected 0, 1 or 2.")

@property
def mma_matrix_shapes(self) -> tuple[int]:
def mma_matrix_shapes(self, mma_type: Optional[MMAType]) -> tuple[int]:
# TODO: Eventually the shapes and indices should be provided by a tool
match self.mma_type:
if mma_type == None:
mma_type = self.mma_type
match mma_type:
case MMAType.F32_16x16x16_F16 | MMAType.I32_16x16x16_I8:
return (16, 16, 16)
case MMAType.F32_32x32x8_F16 | MMAType.I32_32x32x8_I8:
Expand Down Expand Up @@ -179,13 +180,16 @@ def apply(
elements_per_thread: int | IndexSymbol,
stride: int,
is_mma_dim: bool,
mma_type: MMAType,
) -> IndexSequence:
if not is_mma_dim:
return self.compute_access_pattern_using_vector_shapes(
dim, constraint_index, elements_per_thread, stride
)
lane = self.linearized_thread_id % self.threads_per_wave
match self.mma_type:
if mma_type == None:
mma_type = self.mma_type
match mma_type:
# (M x K, N x K) -> M x N
case MMAType.F32_16x16x16_F16 | MMAType.I32_16x16x16_I8:
offset = [
Expand Down Expand Up @@ -248,7 +252,7 @@ def apply(
1, # N
1, # K
]
if self.mma_type == MMAType.F32_16x16x32_K4_F8:
if mma_type == MMAType.F32_16x16x32_K4_F8:
offset = [
Piecewise(
(lane % 16, ~MMA_ACC), (4 * floor(lane / 16), MMA_ACC)
Expand Down Expand Up @@ -282,7 +286,7 @@ def apply(
1, # N
1, # K
]
if self.mma_type == MMAType.F32_32x32x16_K4_F8:
if mma_type == MMAType.F32_32x32x16_K4_F8:
offset = [
Piecewise(
(lane % 32, ~MMA_ACC),
Expand Down
3 changes: 2 additions & 1 deletion iree/turbine/kernel/wave/index_sequence_analysis.py
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Expand Up @@ -439,8 +439,9 @@ def set_node_index(
# dependence in the dimensional index.
# TODO: Evaluate if this is a valid case.
continue
mma_type = anchor.mma_type if anchor else None
index_seq = constraint.apply(
dim, *inputs, anchor and dim in mma_index[anchor]
dim, *inputs, anchor and dim in mma_index[anchor], mma_type
)
if anchor and dim in mma_index[anchor]:
index_seq = specialize_index_sequence(
Expand Down
6 changes: 3 additions & 3 deletions iree/turbine/kernel/wave/utils.py
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Original file line number Diff line number Diff line change
Expand Up @@ -291,9 +291,9 @@ def is_mma(node):
mapping[custom][n] = MMAOperand.N
mapping[custom][k] = MMAOperand.K
custom.vector_shapes = {
m: hardware_constraint.mma_matrix_shapes[0],
n: hardware_constraint.mma_matrix_shapes[1],
k: hardware_constraint.mma_matrix_shapes[2],
m: hardware_constraint.mma_matrix_shapes(custom.mma_type)[0],
n: hardware_constraint.mma_matrix_shapes(custom.mma_type)[1],
k: hardware_constraint.mma_matrix_shapes(custom.mma_type)[2],
}
if hardware_constraint.vector_shapes:
custom.vector_shapes.update(hardware_constraint.vector_shapes)
Expand Down
56 changes: 41 additions & 15 deletions lit_tests/kernel/wave/codegen.py
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Expand Up @@ -1139,12 +1139,12 @@ def test_chained_gemm_32x32x16():
constraints += [tkw.WaveConstraint(M, BLOCK_M / 2)]
constraints += [tkw.WaveConstraint(N, BLOCK_N / 2)]

mfma_variant = tkw.MMAType.F32_32x32x16_F8
mfma_variant = [tkw.MMAType.F32_32x32x16_F8, tkw.MMAType.F32_32x32x16_K4_F8]
constraints += [
tkw.HardwareConstraint(
threads_per_wave=64,
waves_per_block=(2, 2, 1),
mma_type=mfma_variant,
mma_type=mfma_variant[0],
vector_shapes={B: 0},
)
]
Expand Down Expand Up @@ -1172,7 +1172,7 @@ def repeat(
qk_cast_reg = tkw.cast(qk_reg, tkl.f8e4m3fnuz)
v_reg = tkw.read(v, elements_per_thread=LOAD_ELEMS_PER_THREAD)
v_reg = tkw.cast(v_reg, tkl.f8e4m3fnuz)
acc = tkw.mma(qk_cast_reg, v_reg, acc)
acc = tkw.mma(qk_cast_reg, v_reg, acc, mfma_variant[1])
return acc

tkw.write(repeat, c, elements_per_thread=STORE_ELEMS_PER_THREAD)
Expand All @@ -1188,8 +1188,8 @@ def repeat(
BLOCK_N: 64,
BLOCK_K2: 32,
BLOCK_B: 1,
LOAD_ELEMS_PER_THREAD: get_mfma_load_elems_per_thread(mfma_variant),
STORE_ELEMS_PER_THREAD: get_mfma_store_elems_per_thread(mfma_variant),
LOAD_ELEMS_PER_THREAD: get_mfma_load_elems_per_thread(mfma_variant[0]),
STORE_ELEMS_PER_THREAD: get_mfma_store_elems_per_thread(mfma_variant[1]),
ADDRESS_SPACE: SHARED_ADDRESS_SPACE,
ADDRESS_SPACE_0: GLOBAL_ADDRESS_SPACE,
},
Expand All @@ -1202,12 +1202,26 @@ def repeat(
print(chained_gemm_32x32x16(q, k, v, output).module_op)

# CHECK: func.func @chained_gemm_32x32x16(
# CHECK: %[[V_SHARED:.+]] = memref.alloc() : memref<1x64x36xf16, #gpu.address_space<workgroup>>
# CHECK: {{.*}} = scf.for
# 1st MMA
# CHECK-COUNT-4: {{.*}} = arith.truncf
# CHECK-COUNT-2: {{.*}} = amdgpu.mfma
# CHECK-COUNT-3: {{.*}} = arith.truncf
# CHECK: {{.*}} = vector.extract_strided_slice {{.*}} {offsets = [0], sizes = [8], strides = [1]}
# CHECK: {{.*}} = vector.extract_strided_slice {{.*}} {offsets = [8], sizes = [8], strides = [1]}
# CHECK-COUNT-2: {{.*}} = amdgpu.mfma

# Loading V from shared memory with interleaved/k-width=4, then using insert slice to combine them together.
# This is to align V's layout with the layout of 1st MMA output.
# CHECK-COUNT-2: vector.load %[[V_SHARED]]
# CHECK-COUNT-2: %[[V_REG_0:.+]] = vector.insert_strided_slice {{.*}} : vector<4xf16> into vector<8xf16>
# CHECK-COUNT-2: vector.load %[[V_SHARED]]
# CHECK-COUNT-2: %[[V_REG_1:.+]] = vector.insert_strided_slice {{.*}} : vector<4xf16> into vector<8xf16>
# CHECK: %[[V_REG_F8_0:.+]] = arith.truncf %[[V_REG_0]] : vector<8xf16> to vector<8xf8E4M3FNUZ>
# CHECK: %[[V_REG_F8_1:.+]] = arith.truncf %[[V_REG_1]] : vector<8xf16> to vector<8xf8E4M3FNUZ>

# 2nd MMA
# CHECK: %[[QK_REG_0:.+]] = vector.extract_strided_slice {{.*}} {offsets = [0], sizes = [8], strides = [1]}
# CHECK: %[[QK_REG_1:.+]] = vector.extract_strided_slice {{.*}} {offsets = [8], sizes = [8], strides = [1]}
# CHECK: amdgpu.mfma %[[QK_REG_0]] * %[[V_REG_F8_0]]{{.*}} {blocks = 1 : i32, k = 16 : i32, m = 32 : i32, n = 32 : i32} blgp = none : vector<8xf8E4M3FNUZ>, vector<8xf8E4M3FNUZ>, vector<16xf32>
# CHECK: amdgpu.mfma %[[QK_REG_1]] * %[[V_REG_F8_1]]{{.*}} {blocks = 1 : i32, k = 16 : i32, m = 32 : i32, n = 32 : i32} blgp = none : vector<8xf8E4M3FNUZ>, vector<8xf8E4M3FNUZ>, vector<16xf32>
# CHECK: scf.yield


Expand All @@ -1224,12 +1238,12 @@ def test_chained_gemm_16x16x32():
constraints += [tkw.WaveConstraint(M, BLOCK_M / 2)]
constraints += [tkw.WaveConstraint(N, BLOCK_N / 2)]

mfma_variant = tkw.MMAType.F32_16x16x32_F8
mfma_variant = [tkw.MMAType.F32_16x16x32_F8, tkw.MMAType.F32_16x16x32_K4_F8]
constraints += [
tkw.HardwareConstraint(
threads_per_wave=64,
waves_per_block=(2, 2, 1),
mma_type=mfma_variant,
mma_type=mfma_variant[0],
vector_shapes={B: 0},
)
]
Expand Down Expand Up @@ -1257,7 +1271,7 @@ def repeat(
qk_cast_reg = tkw.cast(qk_reg, tkl.f8e4m3fnuz)
v_reg = tkw.read(v, elements_per_thread=LOAD_ELEMS_PER_THREAD)
v_reg = tkw.cast(v_reg, tkl.f8e4m3fnuz)
acc = tkw.mma(qk_cast_reg, v_reg, acc)
acc = tkw.mma(qk_cast_reg, v_reg, acc, mfma_variant[1])
return acc

tkw.write(repeat, c, elements_per_thread=STORE_ELEMS_PER_THREAD)
Expand All @@ -1273,8 +1287,8 @@ def repeat(
BLOCK_N: 64,
BLOCK_K2: 32,
BLOCK_B: 1,
LOAD_ELEMS_PER_THREAD: get_mfma_load_elems_per_thread(mfma_variant),
STORE_ELEMS_PER_THREAD: get_mfma_store_elems_per_thread(mfma_variant),
LOAD_ELEMS_PER_THREAD: get_mfma_load_elems_per_thread(mfma_variant[0]),
STORE_ELEMS_PER_THREAD: get_mfma_store_elems_per_thread(mfma_variant[1]),
ADDRESS_SPACE: SHARED_ADDRESS_SPACE,
ADDRESS_SPACE_0: GLOBAL_ADDRESS_SPACE,
},
Expand All @@ -1287,9 +1301,21 @@ def repeat(
print(chained_gemm_16x16x32(q, k, v, output).module_op)

# CHECK: func.func @chained_gemm_16x16x32(
# CHECK: %[[V_SHARED:.+]] = memref.alloc() : memref<1x64x36xf16, #gpu.address_space<workgroup>>
# CHECK: {{.*}} = scf.for
# 1st MMA
# CHECK-COUNT-4: {{.*}} = arith.truncf
# CHECK-COUNT-4: {{.*}} = amdgpu.mfma
# CHECK-COUNT-6: {{.*}} = arith.truncf

# Loading V from shared memory with interleaved/k-width=4, then using insert slice to combine them together.
# This is to align V's layout with the layout of 1st MMA output.
# CHECK-COUNT-2: vector.load %[[V_SHARED]]
# CHECK-COUNT-2: vector.insert_strided_slice {{.*}} : vector<4xf16> into vector<8xf16>
# CHECK-COUNT-2: vector.load %[[V_SHARED]]
# CHECK-COUNT-2: vector.insert_strided_slice {{.*}} : vector<4xf16> into vector<8xf16>
# CHECK-COUNT-2: arith.truncf {{.*}} : vector<8xf16> to vector<8xf8E4M3FNUZ>

# 2nd MMA
# CHECK: {{.*}} = vector.insert_strided_slice {{.*}} {offsets = [0], strides = [1]}
# CHECK: {{.*}} = vector.insert_strided_slice {{.*}} {offsets = [4], strides = [1]}
# CHECK: {{.*}} = vector.insert_strided_slice {{.*}} {offsets = [0], strides = [1]}
Expand Down
68 changes: 34 additions & 34 deletions lit_tests/kernel/wave/expansion.py
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Expand Up @@ -310,21 +310,21 @@ def test_gemm():
# CHECK-SAME: (%b, 4, None, (), None)

# CHECK-NEXT: %mma_0_0_0
# CHECK-SAME: (%read_0_0_0, %read_0_0_0, %acc_0_0_0)
# CHECK-SAME: (%read_0_0_0, %read_0_0_0, %acc_0_0_0, None)
# CHECK-NEXT: %mma_0_0_1
# CHECK-SAME: (%read_0_0_1, %read_0_0_1, %mma_0_0_0)
# CHECK-SAME: (%read_0_0_1, %read_0_0_1, %mma_0_0_0, None)
# CHECK-NEXT: %mma_1_1_0
# CHECK-SAME: (%read_1_0_0, %read_0_1_0, %acc_1_1_0)
# CHECK-SAME: (%read_1_0_0, %read_0_1_0, %acc_1_1_0, None)
# CHECK-NEXT: %mma_1_1_1
# CHECK-SAME: (%read_1_0_1, %read_0_1_1, %mma_1_1_0)
# CHECK-SAME: (%read_1_0_1, %read_0_1_1, %mma_1_1_0, None)
# CHECK-NEXT: %mma_1_0_0
# CHECK-SAME: (%read_1_0_0, %read_0_0_0, %acc_1_0_0)
# CHECK-SAME: (%read_1_0_0, %read_0_0_0, %acc_1_0_0, None)
# CHECK-NEXT: %mma_1_0_1
# CHECK-SAME: (%read_1_0_1, %read_0_0_1, %mma_1_0_0)
# CHECK-SAME: (%read_1_0_1, %read_0_0_1, %mma_1_0_0, None)
# CHECK-NEXT: %mma_0_1_0
# CHECK-SAME: (%read_0_0_0, %read_0_1_0, %acc_0_1_0)
# CHECK-SAME: (%read_0_0_0, %read_0_1_0, %acc_0_1_0, None)
# CHECK-NEXT: %mma_0_1_1
# CHECK-SAME: (%read_0_0_1, %read_0_1_1, %mma_0_1_0)
# CHECK-SAME: (%read_0_0_1, %read_0_1_1, %mma_0_1_0, None)
# CHECK-NEXT: return [mma_0_0_1, mma_0_1_1, mma_1_0_1, mma_1_1_1]

# Custom format:
Expand Down Expand Up @@ -497,21 +497,21 @@ def test_batched_gemm():
# CHECK-SAME: (%b, 4, None, (), None)

# CHECK-NEXT: %mma_0_0_0
# CHECK-SAME: (%read_0_0_0, %read_0_0_0, %acc_0_0_0)
# CHECK-SAME: (%read_0_0_0, %read_0_0_0, %acc_0_0_0, None)
# CHECK-NEXT: %mma_0_0_1
# CHECK-SAME: (%read_0_0_1, %read_0_0_1, %mma_0_0_0)
# CHECK-SAME: (%read_0_0_1, %read_0_0_1, %mma_0_0_0, None)
# CHECK-NEXT: %mma_1_1_0
# CHECK-SAME: (%read_1_0_0, %read_0_1_0, %acc_1_1_0)
# CHECK-SAME: (%read_1_0_0, %read_0_1_0, %acc_1_1_0, None)
# CHECK-NEXT: %mma_1_1_1
# CHECK-SAME: (%read_1_0_1, %read_0_1_1, %mma_1_1_0)
# CHECK-SAME: (%read_1_0_1, %read_0_1_1, %mma_1_1_0, None)
# CHECK-NEXT: %mma_1_0_0
# CHECK-SAME: (%read_1_0_0, %read_0_0_0, %acc_1_0_0)
# CHECK-SAME: (%read_1_0_0, %read_0_0_0, %acc_1_0_0, None)
# CHECK-NEXT: %mma_1_0_1
# CHECK-SAME: (%read_1_0_1, %read_0_0_1, %mma_1_0_0)
# CHECK-SAME: (%read_1_0_1, %read_0_0_1, %mma_1_0_0, None)
# CHECK-NEXT: %mma_0_1_0
# CHECK-SAME: (%read_0_0_0, %read_0_1_0, %acc_0_1_0)
# CHECK-SAME: (%read_0_0_0, %read_0_1_0, %acc_0_1_0, None)
# CHECK-NEXT: %mma_0_1_1
# CHECK-SAME: (%read_0_0_1, %read_0_1_1, %mma_0_1_0)
# CHECK-SAME: (%read_0_0_1, %read_0_1_1, %mma_0_1_0, None)
# CHECK-NEXT: return [mma_0_0_1, mma_0_1_1, mma_1_0_1, mma_1_1_1]

# Custom format:
Expand Down Expand Up @@ -610,21 +610,21 @@ def test_gemm_non_direct_acc():
# CHECK: %add_0_1_0
# CHECK-SAME: call_function[target=iree.turbine.kernel.ops.wave_ops.add](args = (%exp2_0_0_0, %acc_0_1_0), kwargs = {})
# CHECK: %mma_0_0_0
# CHECK-SAME: call_function[target=iree.turbine.kernel.ops.wave_ops.mma](args = (%read_0_0_0, %read_0_0_0, %add_0_0_0), kwargs = {})
# CHECK-SAME: call_function[target=iree.turbine.kernel.ops.wave_ops.mma](args = (%read_0_0_0, %read_0_0_0, %add_0_0_0, None), kwargs = {})
# CHECK: %mma_0_0_1
# CHECK-SAME: call_function[target=iree.turbine.kernel.ops.wave_ops.mma](args = (%read_0_0_1, %read_0_0_1, %mma_0_0_0), kwargs = {})
# CHECK-SAME: call_function[target=iree.turbine.kernel.ops.wave_ops.mma](args = (%read_0_0_1, %read_0_0_1, %mma_0_0_0, None), kwargs = {})
# CHECK: %mma_1_1_0
# CHECK-SAME: call_function[target=iree.turbine.kernel.ops.wave_ops.mma](args = (%read_1_0_0, %read_0_1_0, %add_1_1_0), kwargs = {})
# CHECK-SAME: call_function[target=iree.turbine.kernel.ops.wave_ops.mma](args = (%read_1_0_0, %read_0_1_0, %add_1_1_0, None), kwargs = {})
# CHECK: %mma_1_1_1
# CHECK-SAME: call_function[target=iree.turbine.kernel.ops.wave_ops.mma](args = (%read_1_0_1, %read_0_1_1, %mma_1_1_0), kwargs = {})
# CHECK-SAME: call_function[target=iree.turbine.kernel.ops.wave_ops.mma](args = (%read_1_0_1, %read_0_1_1, %mma_1_1_0, None), kwargs = {})
# CHECK: %mma_1_0_0
# CHECK-SAME: call_function[target=iree.turbine.kernel.ops.wave_ops.mma](args = (%read_1_0_0, %read_0_0_0, %add_1_0_0), kwargs = {})
# CHECK-SAME: call_function[target=iree.turbine.kernel.ops.wave_ops.mma](args = (%read_1_0_0, %read_0_0_0, %add_1_0_0, None), kwargs = {})
# CHECK: %mma_1_0_1
# CHECK-SAME: call_function[target=iree.turbine.kernel.ops.wave_ops.mma](args = (%read_1_0_1, %read_0_0_1, %mma_1_0_0), kwargs = {})
# CHECK-SAME: call_function[target=iree.turbine.kernel.ops.wave_ops.mma](args = (%read_1_0_1, %read_0_0_1, %mma_1_0_0, None), kwargs = {})
# CHECK: %mma_0_1_0
# CHECK-SAME: call_function[target=iree.turbine.kernel.ops.wave_ops.mma](args = (%read_0_0_0, %read_0_1_0, %add_0_1_0), kwargs = {})
# CHECK-SAME: call_function[target=iree.turbine.kernel.ops.wave_ops.mma](args = (%read_0_0_0, %read_0_1_0, %add_0_1_0, None), kwargs = {})
# CHECK: %mma_0_1_1
# CHECK-SAME: call_function[target=iree.turbine.kernel.ops.wave_ops.mma](args = (%read_0_0_1, %read_0_1_1, %mma_0_1_0), kwargs = {})
# CHECK-SAME: call_function[target=iree.turbine.kernel.ops.wave_ops.mma](args = (%read_0_0_1, %read_0_1_1, %mma_0_1_0, None), kwargs = {})


@tkw.wave_trace_only()
Expand Down Expand Up @@ -739,9 +739,9 @@ def test_gemm_reduction_expansion_only():
# CHECK-SAME: (%b, 4, None, (), None)

# CHECK-NEXT: %mma_0_0_0
# CHECK-SAME: (%read_0_0_0, %read_0_0_0, %acc_0_0_0)
# CHECK-SAME: (%read_0_0_0, %read_0_0_0, %acc_0_0_0, None)
# CHECK-NEXT: %mma_0_0_1
# CHECK-SAME: (%read_0_0_1, %read_0_0_1, %mma_0_0_0)
# CHECK-SAME: (%read_0_0_1, %read_0_0_1, %mma_0_0_0, None)

# CHECK-NEXT: return [mma_0_0_1]

Expand Down Expand Up @@ -932,13 +932,13 @@ def test_chained_gemm_32x32x8():
# CHECK: %read_shared_0_0_3
# CHECK-SAME: (args = (%k, 4, None, (), None)
# CHECK: %mma_0_0_0
# CHECK-SAME: (args = (%read_shared_0_0_0, %read_0_0_0, %register)
# CHECK-SAME: (args = (%read_shared_0_0_0, %read_0_0_0, %register, None)
# CHECK: %mma_0_0_1
# CHECK-SAME: (args = (%read_shared_0_0_1, %read_0_0_1, %mma_0_0_0)
# CHECK-SAME: (args = (%read_shared_0_0_1, %read_0_0_1, %mma_0_0_0, None)
# CHECK: %mma_0_0_2
# CHECK-SAME: (args = (%read_shared_0_0_2, %read_0_0_2, %mma_0_0_1)
# CHECK-SAME: (args = (%read_shared_0_0_2, %read_0_0_2, %mma_0_0_1, None)
# CHECK: %mma_0_0_3
# CHECK-SAME: (args = (%read_shared_0_0_3, %read_0_0_3, %mma_0_0_2)
# CHECK-SAME: (args = (%read_shared_0_0_3, %read_0_0_3, %mma_0_0_2, None)
# CHECK: %permute_0_0
# CHECK-SAME: (args = (%mma_0_0_3, [B, M, K2])
# CHECK: %cast_0_0
Expand All @@ -961,13 +961,13 @@ def test_chained_gemm_32x32x8():
# CHECK: %reshape_0_0_3
# CHECK-SAME: (args = ([%cast_0_0], {K2: 32, M: 32, K1: 8, B: 0})
# CHECK: %mma_0_0_0
# CHECK-SAME: (args = (%reshape_0_0_0, %read_shared_0_0_0, %acc_0_0_0)
# CHECK-SAME: (args = (%reshape_0_0_0, %read_shared_0_0_0, %acc_0_0_0, None)
# CHECK: %mma_0_0_1
# CHECK-SAME: (args = (%reshape_0_0_1, %read_shared_0_0_1, %mma_0_0_0)
# CHECK-SAME: (args = (%reshape_0_0_1, %read_shared_0_0_1, %mma_0_0_0, None)
# CHECK: %mma_0_0_2
# CHECK-SAME: (args = (%reshape_0_0_2, %read_shared_0_0_2, %mma_0_0_1)
# CHECK-SAME: (args = (%reshape_0_0_2, %read_shared_0_0_2, %mma_0_0_1, None)
# CHECK: %mma_0_0_3
# CHECK-SAME: (args = (%reshape_0_0_3, %read_shared_0_0_3, %mma_0_0_2)
# CHECK-SAME: (args = (%reshape_0_0_3, %read_shared_0_0_3, %mma_0_0_2, None)
# CHECK: return [mma_0_0_3]


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2 changes: 1 addition & 1 deletion lit_tests/kernel/wave/promotion.py
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Original file line number Diff line number Diff line change
Expand Up @@ -207,7 +207,7 @@ def test_gemm():
# CHECK-NEXT: %read_3
# CHECK-SAME: (%allocate_1, 4, None, (), [%write_1])
# CHECK-NEXT: %mma
# CHECK-SAME: (%read_2, %read_3, %acc)
# CHECK-SAME: (%read_2, %read_3, %acc, None)


if __name__ == "__main__":
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