FPGA implementation of Ben Eater's 8-bit breadboard computer

This is my humble attempt at implementing Ben Eater's 8-bit breadboard computer in Verilog. For more details about the design and physical hardware implementation of the computer, please refer to the original Youtube playlist.

Building the code

To build and simulate the computer using Verilator, just type:

make

To clean the repository, type

make clean

Overview of the repository

• The directory rtl contains of the Verilog code for the computer, which includes the cpu and the memory;
• The directory data contains the contents of the microcode rom (generated by generate_microcode.py), the initial contents of the ram (including a program to compute Fibonacci numbers), and the contents of the rom for 7-segment display;
• The Verilator code can be found inside sim;
• Inside board\numato_mimas_v2 there are some Verilog files that can be used for generating the bistream for the Numato Mimas V2 board. Among other things, this directory contains the Verilog code for a 7-segment display, a manual clock driver (to throttle the clock to a much smaller frequency, and to enable manual control of the clock frequency);

Thank you Ben Eater for the awesome videos!!!