feat: add ANI and ORI command

hemanta212 · Mar 6, 2022 · 4afabc8 · 4afabc8
1 parent da02310
commit 4afabc8
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diff --git a/command_model.py b/command_model.py
@@ -242,6 +242,46 @@ def compare(self, args: tuple) -> None:
             f"\nFLAGS: CY->{int(self.state.flags['carry'])}, S->{int(self.state.flags['sign'])}, Z->{int(self.state.flags['zero'])}"
         )
 
+    def and_immediate(self, args: tuple) -> None:
+        """
+        Bitwise Logical AND with accumulator and 8 byte data
+        """
+        logger.debug(f"AND Immediate: {args}")
+        value = args[0]
+        formatted_value = f"0x{int(value, 16):02x}"
+        acc_value = self.state.accumulator
+        result = int(acc_value, 16) & int(value, 16)
+        self.change_state_flags(zero=True if result == 0 else False)
+        self.state.accumulator = f"0x{result:02x}"
+        logger.debug(f"{value} AND {acc_value} -> {result}:{self.state.accumulator}")
+        print(
+            f"{hex_to_simple(acc_value)} & {hex_to_simple(formatted_value)} -> {hex_to_simple(self.state.accumulator)}"
+        )
+        if self.state.flags["zero"]:
+            print(
+                f"FLAGS: CY->{int(self.state.flags['carry'])}, S->{int(self.state.flags['sign'])}, Z->{int(self.state.flags['zero'])}"
+            )
+
+    def or_immediate(self, args: tuple) -> None:
+        """
+        Bitwise Logical OR with accumulator and 8 byte data
+        """
+        logger.debug(f"OR Immediate: {args}")
+        value = args[0]
+        formatted_value = f"0x{int(value, 16):02x}"
+        acc_value = self.state.accumulator
+        result = int(acc_value, 16) | int(value, 16)
+        self.change_state_flags(zero=True if result == 0 else False)
+        self.state.accumulator = f"0x{result:02x}"
+        logger.debug(f"{value} OR {acc_value} -> {result}:{self.state.accumulator}")
+        print(
+            f"{hex_to_simple(acc_value)} & {hex_to_simple(formatted_value)} -> {hex_to_simple(self.state.accumulator)}"
+        )
+        if self.state.flags["zero"]:
+            print(
+                f"FLAGS: CY->{int(self.state.flags['carry'])}, S->{int(self.state.flags['sign'])}, Z->{int(self.state.flags['zero'])}"
+            )
+
     def increment_register(self, args: tuple) -> None:
         """
         Increment a given register by 1

diff --git a/data.py b/data.py
@@ -120,6 +120,20 @@
             "value": "byte",
         },
     },
+    "ANI": {
+        "description": "And Immediate with Accumulator",
+        "function": "and_immediate",
+        "parameters": {
+            "value": "byte",
+        },
+    },
+    "ORI": {
+        "description": "OR Immediate with Accumulator",
+        "function": "or_immediate",
+        "parameters": {
+            "value": "byte",
+        },
+    },
     "LDAX": {
         "description": "Load accumulator from register pair",
         "function": "load_accumulator_from_register_pair",

diff --git a/usage_examples.org b/usage_examples.org
@@ -403,6 +403,44 @@ For other we have to manually load the value to Accumulator
 : A -> 0AH  ; FROM DE -> [0x1260]
 : A: 0AH
 
+** ANI
+#+begin_src 8085 :export both :args -db /tmp/8085-session1
+  MVI A 79H
+  ANI 80H
+  OUT A
+  MVI A 90H
+  ANI 80H
+#+end_src
+
+#+RESULTS:
+: A -> 79H
+: 79H & 80H -> 00H
+: FLAGS: CY->0, S->0, Z->1
+: A: 00H
+: A -> 90H
+: 90H & 80H -> 80H
+
+** ORI
+#+begin_src 8085 :export both :args -db /tmp/8085-session1
+  MVI A 02H
+  ORI 01H
+  OUT A
+  MVI A 02H
+  ORI 05H
+  MVI A 0H
+  ORI 0H
+#+end_src
+
+#+RESULTS:
+: A -> 02H
+: 02H | 01H -> 03H
+: A: 03H
+: A -> 02H
+: 02H | 05H -> 07H
+: A -> 00H
+: 00H | 00H -> 00H
+: FLAGS: CY->0, S->0, Z->1
+
 * Practice Problems
 ** Register setup from 1260 to 1264
 #+begin_src 8085 :args -db /tmp/8085-session1 :exports both