Add byte/uchar version of verilog block (#3)

Signed-off-by: Jeppe Johansen <jgj@gomspace.com>

README.md

@@ -6,7 +6,7 @@
 
 This is an OOT module for GNU Radio integrating verilog simulation. This module can run Verilog simulation at runtime in GNU Radio based on [Verilator](https://www.veripool.org/wiki/verilator/), an open-source Verilog simulator.
 
-So far, serveral blocks namely `verilog_axi_ii`, `verilog_axi_ff`, `verilog_axi_ss` and `verilog_axi_cc`, hereinafter referred to as `verilog_axi_xx`, were implemented.
+So far, serveral blocks namely `verilog_axi_ii`, `verilog_axi_ff`, `verilog_axi_ss`, `verilog_axi_bb` and `verilog_axi_cc`, hereinafter referred to as `verilog_axi_xx`, were implemented.
 
 The `verilog_axi_xx` block can be used in both python code or GNU Radio Companion.
 

grc/verilog_verilog_axi_xx.xml

@@ -34,6 +34,11 @@
       <key>short</key>
       <opt>fcn:ss</opt>
     </option>
+    <option>
+      <name>Byte</name>
+      <key>byte</key>
+      <opt>fcn:bb</opt>
+    </option>
   </param>
   <param>
     <name>Overwrite</name>

grc/verilog_verilog_axi_xx.yml

@@ -9,9 +9,9 @@ parameters:
 -   id: type
     label: IO Type
     dtype: enum
-    options: [complex, float, int, short]
+    options: [complex, float, int, short, byte]
     option_attributes:
-        fcn: [cc, ff, ii, ss]
+        fcn: [cc, ff, ii, ss, bb]
     hide: part
 -   id: overwrite
     label: Overwrite

include/verilog/CMakeLists.txt

@@ -25,5 +25,6 @@ install(FILES
     verilog_axi_ii.h
     verilog_axi_ff.h
     verilog_axi_ss.h
+    verilog_axi_bb.h
     verilog_axi_cc.h DESTINATION include/verilog
 )

include/verilog/verilog_axi_bb.h

@@ -0,0 +1,58 @@
+/* -*- c++ -*- */
+/* 
+ * Copyright 2019 <+YOU OR YOUR COMPANY+>.
+ * 
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+ * 
+ * This software is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this software; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+
+#ifndef INCLUDED_VERILOG_VERILOG_AXI_BB_H
+#define INCLUDED_VERILOG_VERILOG_AXI_BB_H
+
+#include <verilog/api.h>
+#include <gnuradio/block.h>
+
+namespace gr {
+  namespace verilog {
+
+    /*!
+     * \brief <+description of block+>
+     * \ingroup verilog
+     *
+     */
+    class VERILOG_API verilog_axi_bb : virtual public gr::block
+    {
+     public:
+      typedef boost::shared_ptr<verilog_axi_bb> sptr;
+
+      /*!
+       * \brief Return a shared_ptr to a new instance of verilog::verilog_axi_bb.
+       *
+       * To avoid accidental use of raw pointers, verilog::verilog_axi_bb's
+       * constructor is in a private implementation
+       * class. verilog::verilog_axi_bb::make is the public interface for
+       * creating new instances.
+       */
+      static sptr make(const char *filename, bool overwrite, float IO_ratio,
+                       const char *verilator_options, unsigned int module_flag,
+                       unsigned int skip_output_items);
+    };
+
+  } // namespace verilog
+} // namespace gr
+
+#endif /* INCLUDED_VERILOG_VERILOG_AXI_BB_H */
+

lib/CMakeLists.txt

@@ -33,6 +33,7 @@ list(APPEND verilog_sources
     Shared_lib.cpp
     verilog_axi_ff_impl.cc
     verilog_axi_ss_impl.cc
+    verilog_axi_bb_impl.cc
     verilog_axi_cc_impl.cc
 )