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[RISCV] Modify Makefile and Add a RISCV_VECT to print log info #9442

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merged 1 commit into from
Sep 12, 2024

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Tameem-10xE
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The log will now show RISCV_VECT=1 if the RVV processor is detected. Additionally, I've updated the Makefile to eliminate the need for a specific flag for RISC-V vector boards. Now, only the RISCV_CROSS_COMPILATION=1 flag with makefile is required for running with the emulator (e.g., QEMU).

- Added ggml_cpu_has_riscv_v() in GGML to print system info in log
- Modified Makefile to only use flag when cross compiling for RISC-V
@github-actions github-actions bot added the ggml changes relating to the ggml tensor library for machine learning label Sep 11, 2024
@ggerganov ggerganov merged commit 2b00fa7 into ggerganov:master Sep 12, 2024
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@grigohas
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Hello, is llama-embedding working for that riscv impl or only the llam-cli ?

dsx1986 pushed a commit to dsx1986/llama.cpp that referenced this pull request Oct 29, 2024
…anov#9442)

- Added ggml_cpu_has_riscv_v() in GGML to print system info in log
- Modified Makefile to only use flag when cross compiling for RISC-V
arthw pushed a commit to arthw/llama.cpp that referenced this pull request Nov 15, 2024
…anov#9442)

- Added ggml_cpu_has_riscv_v() in GGML to print system info in log
- Modified Makefile to only use flag when cross compiling for RISC-V
arthw pushed a commit to arthw/llama.cpp that referenced this pull request Nov 18, 2024
…anov#9442)

- Added ggml_cpu_has_riscv_v() in GGML to print system info in log
- Modified Makefile to only use flag when cross compiling for RISC-V
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3 participants