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CORE-V: Support Multiply Accumulate Extension #92

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CORE-V: Support Multiply Accumulate Extension #92

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e35fa28
CORE-V: MAC builtins added
Jan 10, 2023
40e97b3
CORE-V: Update extension name prefix from 'xcorev' to 'xcv'
Feb 22, 2023
3a7f4a0
CORE-V: Remove 'xcv' extension
Feb 22, 2023
9a9f9a0
CORE-V: Removed Implicit ISA info and added compile tests
NandniJamnadas Feb 27, 2023
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2 changes: 2 additions & 0 deletions gcc/common/config/riscv/riscv-common.cc
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Expand Up @@ -276,6 +276,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
{"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
{"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
{"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},

/* Terminate the list. */
{NULL, ISA_SPEC_CLASS_NONE, 0, 0}
Expand Down Expand Up @@ -1419,6 +1420,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"xtheadmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX},
{"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
{"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
{"xcvmac", &gcc_options::x_riscv_xcv_flags, MASK_XCVMAC},

{NULL, NULL, 0}
};
Expand Down
19 changes: 19 additions & 0 deletions gcc/config/riscv/corev.def
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@@ -0,0 +1,19 @@
// XCVMAC
RISCV_BUILTIN (cv_mac_mac, "cv_mac_mac", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_SI, cvmac),
RISCV_BUILTIN (cv_mac_msu, "cv_mac_msu", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_SI, cvmac),
RISCV_BUILTIN (cv_mac_muluN, "cv_mac_muluN", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvmac),
RISCV_BUILTIN (cv_mac_mulhhuN, "cv_mac_mulhhuN", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvmac),
RISCV_BUILTIN (cv_mac_mulsN, "cv_mac_mulsN", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_UQI, cvmac),
RISCV_BUILTIN (cv_mac_mulhhsN, "cv_mac_mulhhsN", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_UQI, cvmac),
RISCV_BUILTIN (cv_mac_muluRN, "cv_mac_muluRN", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvmac),
RISCV_BUILTIN (cv_mac_mulhhuRN, "cv_mac_mulhhuRN", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_UQI, cvmac),
RISCV_BUILTIN (cv_mac_mulsRN, "cv_mac_mulsRN", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_UQI, cvmac),
RISCV_BUILTIN (cv_mac_mulhhsRN, "cv_mac_mulhhsRN", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_UQI, cvmac),
RISCV_BUILTIN (cv_mac_macuN, "cv_mac_macuN", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI_UQI, cvmac),
RISCV_BUILTIN (cv_mac_machhuN, "cv_mac_machhuN", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI_UQI, cvmac),
RISCV_BUILTIN (cv_mac_macsN, "cv_mac_macsN", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_SI_UQI, cvmac),
RISCV_BUILTIN (cv_mac_machhsN, "cv_mac_machhsN", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_SI_UQI, cvmac),
RISCV_BUILTIN (cv_mac_macuRN, "cv_mac_macuRN", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI_UQI, cvmac),
RISCV_BUILTIN (cv_mac_machhuRN, "cv_mac_machhuRN", RISCV_BUILTIN_DIRECT, RISCV_USI_FTYPE_USI_USI_USI_UQI, cvmac),
RISCV_BUILTIN (cv_mac_macsRN, "cv_mac_macsRN", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_SI_UQI, cvmac),
RISCV_BUILTIN (cv_mac_machhsRN, "cv_mac_machhsRN", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_SI_UQI, cvmac),
264 changes: 264 additions & 0 deletions gcc/config/riscv/corev.md
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@@ -0,0 +1,264 @@
;; Machine description for RISC-V MAC operations.
;; Copyright (C) 2023 Free Software Foundation, Inc.

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.

;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.

(define_insn "riscv_cv_mac_mac"
[(set (match_operand:SI 0 "register_operand" "=r")
(fma:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r")
(match_operand:SI 3 "register_operand" "0")))]

"TARGET_XCVMAC && !TARGET_64BIT"
"cv.mac\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])

(define_insn "riscv_cv_mac_msu"
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (match_operand:SI 3 "register_operand" "0")
(mult:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "register_operand" "r"))))]

"TARGET_XCVMAC && !TARGET_64BIT"
"cv.msu\t%0,%1,%2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])

(define_insn "riscv_cv_mac_muluN"
[(set (match_operand:SI 0 "register_operand" "=r")
(lshiftrt:SI (mult:SI (zero_extend:SI (truncate:HI (match_operand:SI 1 "register_operand" "r")))
(zero_extend:SI (truncate:HI (match_operand:SI 2 "register_operand" "r"))))
(match_operand:QI 3 "const_csr_operand" "K")))]

"TARGET_XCVMAC && !TARGET_64BIT"
"cv.muluN\t%0,%1,%2,%3"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])

(define_insn "riscv_cv_mac_mulhhuN"
[(set (match_operand:SI 0 "register_operand" "=r")
(lshiftrt:SI (mult:SI (zero_extend:SI (truncate:HI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") (const_int 16))))
(zero_extend:SI (truncate:HI (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") (const_int 16)))))
(match_operand:QI 3 "const_csr_operand" "K")))]

"TARGET_XCVMAC && !TARGET_64BIT"
"cv.mulhhuN\t%0,%1,%2,%3"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])

(define_insn "riscv_cv_mac_mulsN"
[(set (match_operand:SI 0 "register_operand" "=r")
(ashiftrt:SI (mult:SI (sign_extend:SI (truncate:HI (match_operand:SI 1 "register_operand" "r")))
(sign_extend:SI (truncate:HI (match_operand:SI 2 "register_operand" "r"))))
(match_operand:QI 3 "const_csr_operand" "K")))]

"TARGET_XCVMAC && !TARGET_64BIT"
"cv.mulsN\t%0,%1,%2,%3"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])

(define_insn "riscv_cv_mac_mulhhsN"
[(set (match_operand:SI 0 "register_operand" "=r")
(ashiftrt:SI (mult:SI (sign_extend:SI (truncate:HI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") (const_int 16))))
(sign_extend:SI (truncate:HI (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") (const_int 16)))))
(match_operand:QI 3 "const_csr_operand" "K")))]

"TARGET_XCVMAC && !TARGET_64BIT"
"cv.mulhhsN\t%0,%1,%2,%3"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])

(define_insn "riscv_cv_mac_muluRN"
[(set (match_operand:SI 0 "register_operand" "=r")
(lshiftrt:SI (fma:SI (zero_extend:SI (truncate:HI (match_operand:SI 1 "register_operand" "r")))
(zero_extend:SI (truncate:HI (match_operand:SI 2 "register_operand" "r")))
(if_then_else (ne:QI (match_operand:QI 3 "const_csr_operand" "K") (const_int 0))
(ashift:SI (const_int 1)
(minus:QI (match_dup 3)
(const_int 1)))
(const_int 0)))
(match_dup 3)))]

"TARGET_XCVMAC && !TARGET_64BIT"
"cv.muluRN\t%0,%1,%2,%3"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])

(define_insn "riscv_cv_mac_mulhhuRN"
[(set (match_operand:SI 0 "register_operand" "=r")
(lshiftrt:SI (fma:SI (zero_extend:SI (truncate:HI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") (const_int 16))))
(zero_extend:SI (truncate:HI (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") (const_int 16))))
(if_then_else (ne:QI (match_operand:QI 3 "const_csr_operand" "K") (const_int 0))
(ashift:SI (const_int 1)
(minus:QI (match_dup 3)
(const_int 1)))
(const_int 0)))
(match_dup 3)))]

"TARGET_XCVMAC && !TARGET_64BIT"
"cv.mulhhuRN\t%0,%1,%2,%3"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])

(define_insn "riscv_cv_mac_mulsRN"
[(set (match_operand:SI 0 "register_operand" "=r")
(ashiftrt:SI (fma:SI (sign_extend:SI (truncate:HI (match_operand:SI 1 "register_operand" "r")))
(sign_extend:SI (truncate:HI (match_operand:SI 2 "register_operand" "r")))
(if_then_else (ne:QI (match_operand:QI 3 "const_csr_operand" "K") (const_int 0))
(ashift:SI (const_int 1)
(minus:QI (match_dup 3)
(const_int 1)))
(const_int 0)))
(match_dup 3)))]

"TARGET_XCVMAC && !TARGET_64BIT"
"cv.mulsRN\t%0,%1,%2,%3"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])

(define_insn "riscv_cv_mac_mulhhsRN"
[(set (match_operand:SI 0 "register_operand" "=r")
(ashiftrt:SI (fma:SI (sign_extend:SI (truncate:HI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") (const_int 16))))
(sign_extend:SI (truncate:HI (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") (const_int 16))))
(if_then_else (ne:QI (match_operand:QI 3 "const_csr_operand" "K") (const_int 0))
(ashift:SI (const_int 1)
(minus:QI (match_dup 3)
(const_int 1)))
(const_int 0)))
(match_dup 3)))]

"TARGET_XCVMAC && !TARGET_64BIT"
"cv.mulhhsRN\t%0,%1,%2,%3"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])

(define_insn "riscv_cv_mac_macuN"
[(set (match_operand:SI 0 "register_operand" "=r")
(lshiftrt:SI (fma:SI (zero_extend:SI (truncate:HI (match_operand:SI 1 "register_operand" "r")))
(zero_extend:SI (truncate:HI (match_operand:SI 2 "register_operand" "r")))
(match_operand:SI 3 "register_operand" "0"))
(match_operand:QI 4 "const_csr_operand" "K")))]

"TARGET_XCVMAC && !TARGET_64BIT"
"cv.macuN\t%0,%1,%2,%4"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])

(define_insn "riscv_cv_mac_machhuN"
[(set (match_operand:SI 0 "register_operand" "=r")
(lshiftrt:SI (fma:SI (zero_extend:SI (truncate:HI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") (const_int 16))))
(zero_extend:SI (truncate:HI (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") (const_int 16))))
(match_operand:SI 3 "register_operand" "0"))
(match_operand:QI 4 "const_csr_operand" "K")))]

"TARGET_XCVMAC && !TARGET_64BIT"
"cv.machhuN\t%0,%1,%2,%4"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])

(define_insn "riscv_cv_mac_macsN"
[(set (match_operand:SI 0 "register_operand" "=r")
(ashiftrt:SI (fma:SI (sign_extend:SI (truncate:HI (match_operand:SI 1 "register_operand" "r")))
(sign_extend:SI (truncate:HI (match_operand:SI 2 "register_operand" "r")))
(match_operand:SI 3 "register_operand" "0"))
(match_operand:QI 4 "const_csr_operand" "K")))]

"TARGET_XCVMAC && !TARGET_64BIT"
"cv.macsN\t%0,%1,%2,%4"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])

(define_insn "riscv_cv_mac_machhsN"
[(set (match_operand:SI 0 "register_operand" "=r")
(ashiftrt:SI (fma:SI (sign_extend:SI (truncate:HI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") (const_int 16))))
(sign_extend:SI (truncate:HI (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") (const_int 16))))
(match_operand:SI 3 "register_operand" "0"))
(match_operand:QI 4 "const_csr_operand" "K")))]

"TARGET_XCVMAC && !TARGET_64BIT"
"cv.machhsN\t%0,%1,%2,%4"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])

(define_insn "riscv_cv_mac_macuRN"
[(set (match_operand:SI 0 "register_operand" "=r")
(lshiftrt:SI (plus:SI (fma:SI (zero_extend:SI (truncate:HI (match_operand:SI 1 "register_operand" "r")))
(zero_extend:SI (truncate:HI (match_operand:SI 2 "register_operand" "r")))
(match_operand:SI 3 "register_operand" "0"))
(if_then_else (ne:QI (match_operand:QI 4 "const_csr_operand" "K") (const_int 0))
(ashift:SI (const_int 1)
(minus:QI (match_dup 4)
(const_int 1)))
(const_int 0)))
(match_dup 4)))]

"TARGET_XCVMAC && !TARGET_64BIT"
"cv.macuRN\t%0,%1,%2,%4"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])

(define_insn "riscv_cv_mac_machhuRN"
[(set (match_operand:SI 0 "register_operand" "=r")
(lshiftrt:SI (plus:SI (fma:SI (zero_extend:SI (truncate:HI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") (const_int 16))))
(zero_extend:SI (truncate:HI (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") (const_int 16))))
(match_operand:SI 3 "register_operand" "0"))
(if_then_else (ne:QI (match_operand:QI 4 "const_csr_operand" "K") (const_int 0))
(ashift:SI (const_int 1)
(minus:QI (match_dup 4)
(const_int 1)))
(const_int 0)))
(match_dup 4)))]

"TARGET_XCVMAC && !TARGET_64BIT"
"cv.machhuRN\t%0,%1,%2,%4"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])

(define_insn "riscv_cv_mac_macsRN"
[(set (match_operand:SI 0 "register_operand" "=r")
(ashiftrt:SI (plus:SI (fma:SI (sign_extend:SI (truncate:HI (match_operand:SI 1 "register_operand" "r")))
(sign_extend:SI (truncate:HI (match_operand:SI 2 "register_operand" "r")))
(match_operand:SI 3 "register_operand" "0"))
(if_then_else (ne:QI (match_operand:QI 4 "const_csr_operand" "K") (const_int 0))
(ashift:SI (const_int 1)
(minus:QI (match_dup 4)
(const_int 1)))
(const_int 0)))
(match_dup 4)))]

"TARGET_XCVMAC && !TARGET_64BIT"
"cv.macsRN\t%0,%1,%2,%4"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])

(define_insn "riscv_cv_mac_machhsRN"
[(set (match_operand:SI 0 "register_operand" "=r")
(ashiftrt:SI (plus:SI (fma:SI (sign_extend:SI (truncate:HI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") (const_int 16))))
(sign_extend:SI (truncate:HI (lshiftrt:SI (match_operand:SI 2 "register_operand" "r") (const_int 16))))
(match_operand:SI 3 "register_operand" "0"))
(if_then_else (ne:QI (match_operand:QI 4 "const_csr_operand" "K") (const_int 0))
(ashift:SI (const_int 1)
(minus:QI (match_dup 4)
(const_int 1)))
(const_int 0)))
(match_dup 4)))]

"TARGET_XCVMAC && !TARGET_64BIT"
"cv.machhsRN\t%0,%1,%2,%4"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
10 changes: 10 additions & 0 deletions gcc/config/riscv/riscv-builtins.cc
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Expand Up @@ -47,6 +47,8 @@ along with GCC; see the file COPYING3. If not see
#define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B
#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C
#define RISCV_FTYPE_NAME3(A, B, C, D) RISCV_##A##_FTYPE_##B##_##C##_##D
#define RISCV_FTYPE_NAME4(A, B, C, D, E) \
RISCV_##A##_FTYPE_##B##_##C##_##D##_##E

/* Classifies the prototype of a built-in function. */
enum riscv_function_type {
Expand Down Expand Up @@ -124,6 +126,9 @@ AVAIL (clmulr_zbc32, TARGET_ZBC && !TARGET_64BIT)
AVAIL (clmulr_zbc64, TARGET_ZBC && TARGET_64BIT)
AVAIL (always, (!0))

//COREV AVAIL
AVAIL (cvmac, TARGET_XCVMAC && !TARGET_64BIT)

/* Construct a riscv_builtin_description from the given arguments.

INSN is the name of the associated instruction pattern, without the
Expand Down Expand Up @@ -155,6 +160,7 @@ AVAIL (always, (!0))

/* Argument types. */
#define RISCV_ATYPE_VOID void_type_node
#define RISCV_ATYPE_UQI unsigned_intQI_type_node
#define RISCV_ATYPE_USI unsigned_intSI_type_node
#define RISCV_ATYPE_QI intQI_type_node
#define RISCV_ATYPE_HI intHI_type_node
Expand All @@ -172,10 +178,14 @@ AVAIL (always, (!0))
RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C
#define RISCV_FTYPE_ATYPES3(A, B, C, D) \
RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D
#define RISCV_FTYPE_ATYPES4(A, B, C, D, E) \
RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D, \
RISCV_ATYPE_##E

static const struct riscv_builtin_description riscv_builtins[] = {
#include "riscv-cmo.def"
#include "riscv-scalar-crypto.def"
#include "corev.def"

DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float),
Expand Down
4 changes: 4 additions & 0 deletions gcc/config/riscv/riscv-ftypes.def
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Expand Up @@ -42,3 +42,7 @@ DEF_RISCV_FTYPE (2, (DI, DI, SI))
DEF_RISCV_FTYPE (2, (DI, DI, DI))
DEF_RISCV_FTYPE (3, (SI, SI, SI, SI))
DEF_RISCV_FTYPE (3, (DI, DI, DI, SI))
DEF_RISCV_FTYPE (3, (USI, USI, USI, UQI)) //RISCV_USI_FTYPE_USI_USI_UQI
DEF_RISCV_FTYPE (3, (SI, SI, SI, UQI)) //RISCV_SI_FTYPE_SI_SI_UQI
DEF_RISCV_FTYPE (4, (USI, USI, USI, USI, UQI)) //RISCV_USI_FTYPE_USI_USI_USI_UQI
DEF_RISCV_FTYPE (4, (SI, SI, SI, SI, UQI)) //RISCV_SI_FTYPE_SI_SI_SI_UQI
4 changes: 4 additions & 0 deletions gcc/config/riscv/riscv-opts.h
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Expand Up @@ -298,4 +298,8 @@ enum riscv_entity
is the highest priority choice and should not conflict with VLS modes. */
#define TARGET_VECTOR_VLS (riscv_autovec_preference == RVV_SCALABLE)

#define MASK_XCVMAC (1 << 0)

#define TARGET_XCVMAC ((riscv_xcv_flags & MASK_XCVMAC) != 0)

#endif /* ! GCC_RISCV_OPTS_H */
13 changes: 1 addition & 12 deletions gcc/config/riscv/riscv.md
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Expand Up @@ -3288,18 +3288,6 @@
"TARGET_XTHEADBB"
)

(define_expand "extzv<mode>"
[(set (match_operand:GPR 0 "register_operand" "=r")
(zero_extract:GPR (match_operand:GPR 1 "register_operand" "r")
(match_operand 2 "const_int_operand")
(match_operand 3 "const_int_operand")))]
"TARGET_XTHEADBB"
{
if (TARGET_XTHEADBB
&& (INTVAL (operands[2]) < 8) && (INTVAL (operands[3]) == 0))
FAIL;
})

(define_expand "maddhisi4"
[(set (match_operand:SI 0 "register_operand")
(plus:SI
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(include "thead.md")
(include "vector.md")
(include "zicond.md")
(include "corev.md")
3 changes: 3 additions & 0 deletions gcc/config/riscv/riscv.opt
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Expand Up @@ -248,6 +248,9 @@ int riscv_sv_subext
TargetVariable
int riscv_xthead_subext

TargetVariable
int riscv_xcv_flags

Enum
Name(isa_spec_class) Type(enum riscv_isa_spec_class)
Supported ISA specs (for use with the -misa-spec= option):
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