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net: emac: emac gigabit ethernet controller driver
Add support for the Qualcomm Technologies, Inc. EMAC gigabit Ethernet controller. This driver supports the following features: 1) Checksum offload. 2) Interrupt coalescing support. 3) SGMII phy. 4) phylib interface for external phy Based on original work by Niranjana Vishwanathapura <nvishwan@codeaurora.org> Gilad Avidov <gavidov@codeaurora.org> Signed-off-by: Timur Tabi <timur@codeaurora.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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Qualcomm Technologies EMAC Gigabit Ethernet Controller | ||
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This network controller consists of two devices: a MAC and an SGMII | ||
internal PHY. Each device is represented by a device tree node. A phandle | ||
connects the MAC node to its corresponding internal phy node. Another | ||
phandle points to the external PHY node. | ||
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Required properties: | ||
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MAC node: | ||
- compatible : Should be "qcom,fsm9900-emac". | ||
- reg : Offset and length of the register regions for the device | ||
- interrupts : Interrupt number used by this controller | ||
- mac-address : The 6-byte MAC address. If present, it is the default | ||
MAC address. | ||
- internal-phy : phandle to the internal PHY node | ||
- phy-handle : phandle the the external PHY node | ||
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Internal PHY node: | ||
- compatible : Should be "qcom,fsm9900-emac-sgmii" or "qcom,qdf2432-emac-sgmii". | ||
- reg : Offset and length of the register region(s) for the device | ||
- interrupts : Interrupt number used by this controller | ||
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The external phy child node: | ||
- reg : The phy address | ||
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Example: | ||
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FSM9900: | ||
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soc { | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
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emac0: ethernet@feb20000 { | ||
compatible = "qcom,fsm9900-emac"; | ||
reg = <0xfeb20000 0x10000>, | ||
<0xfeb36000 0x1000>; | ||
interrupts = <76>; | ||
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clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>, | ||
<&gcc 6>, <&gcc 7>; | ||
clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk", | ||
"mdio_clk", "tx_clk", "rx_clk", "sys_clk"; | ||
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internal-phy = <&emac_sgmii>; | ||
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phy-handle = <&phy0>; | ||
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#address-cells = <1>; | ||
#size-cells = <0>; | ||
phy0: ethernet-phy@0 { | ||
reg = <0>; | ||
}; | ||
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pinctrl-names = "default"; | ||
pinctrl-0 = <&mdio_pins_a>; | ||
}; | ||
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emac_sgmii: ethernet@feb38000 { | ||
compatible = "qcom,fsm9900-emac-sgmii"; | ||
reg = <0xfeb38000 0x1000>; | ||
interrupts = <80>; | ||
}; | ||
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tlmm: pinctrl@fd510000 { | ||
compatible = "qcom,fsm9900-pinctrl"; | ||
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mdio_pins_a: mdio { | ||
state { | ||
pins = "gpio123", "gpio124"; | ||
function = "mdio"; | ||
}; | ||
}; | ||
}; | ||
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QDF2432: | ||
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soc { | ||
#address-cells = <2>; | ||
#size-cells = <2>; | ||
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emac0: ethernet@38800000 { | ||
compatible = "qcom,fsm9900-emac"; | ||
reg = <0x0 0x38800000 0x0 0x10000>, | ||
<0x0 0x38816000 0x0 0x1000>; | ||
interrupts = <0 256 4>; | ||
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clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>, | ||
<&gcc 6>, <&gcc 7>; | ||
clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk", | ||
"mdio_clk", "tx_clk", "rx_clk", "sys_clk"; | ||
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internal-phy = <&emac_sgmii>; | ||
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phy-handle = <&phy0>; | ||
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#address-cells = <1>; | ||
#size-cells = <0>; | ||
phy0: ethernet-phy@4 { | ||
reg = <4>; | ||
}; | ||
}; | ||
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emac_sgmii: ethernet@410400 { | ||
compatible = "qcom,qdf2432-emac-sgmii"; | ||
reg = <0x0 0x00410400 0x0 0xc00>, /* Base address */ | ||
<0x0 0x00410000 0x0 0x400>; /* Per-lane digital */ | ||
interrupts = <0 254 1>; | ||
}; |
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obj-$(CONFIG_QCA7000) += qcaspi.o | ||
qcaspi-objs := qca_spi.o qca_framing.o qca_7k.o qca_debug.o | ||
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obj-y += emac/ |
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# | ||
# Makefile for the Qualcomm Technologies, Inc. EMAC Gigabit Ethernet driver | ||
# | ||
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obj-$(CONFIG_QCOM_EMAC) += qcom-emac.o | ||
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qcom-emac-objs := emac.o emac-mac.o emac-phy.o emac-sgmii.o |
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