Merge pull request #1 from GiuseppeDiGuglielmo/dev

Add data from board runs (demo00/send_receive_pulse)

.gitignore

@@ -142,7 +142,7 @@ checkpoints/
 results/
 
 # other extensions 
-*.h5
+#*.h5
 *.npy
 *.txt
 *.png
@@ -158,4 +158,4 @@ hls4ml/
 notebooks/3*
 tmp*/
 hls4ml_prj/
-*wrapper/
+*wrapper/

create_env.sh

@@ -0,0 +1 @@
+conda env create -f environment.yml

data/fpga_testing/README.md

@@ -0,0 +1,7 @@
+# Data
+
+Data recorded on the board:
+- demo00/send_receive_pulse `X_fpga.csv`, `y_fpga.csv`
+- Mock readout data
+  - excited state`malab_e_state_X_fpga.csv`, `malab_e_state_y_fpga.csv`
+  - ground state `malab_g_state_X_fpga.csv`, `malab_g_state_y_fpga.csv`

data/qick_data/.gitignore

@@ -0,0 +1,5 @@
+00000000
+20230529
+20240501
+20240527
+20240528

data/qick_data/generate_window.py

@@ -0,0 +1,54 @@
+import os
+import argparse
+import numpy as np
+
+parser = argparse.ArgumentParser()
+
+parser.add_argument('--in_lo', type=int, default=0, help='Input low range (default: 0)')
+parser.add_argument('--in_hi', type=int, default=770, help='Input high range (default: 770)')
+parser.add_argument('--ou_lo', type=int, required=True, help='Output low range')
+parser.add_argument('--ou_hi', type=int, required=True, help='Output high range')
+
+args = parser.parse_args()
+
+IN_LO = args.in_lo
+IN_HI = args.in_hi
+
+OU_LO = args.ou_lo
+OU_HI = args.ou_hi
+
+print('{:03d}_{:03d} --> {:03d}_{:03d}'.format(IN_LO, IN_HI, OU_LO, OU_HI))
+
+X_train = np.load('{:03d}_{:03d}/X_train_{:03d}_{:03d}.npy'.format(IN_LO, IN_HI, IN_LO, IN_HI))
+y_train = np.load('{:03d}_{:03d}/y_train_{:03d}_{:03d}.npy'.format(IN_LO, IN_HI, IN_LO, IN_HI))
+X_test = np.load('{:03d}_{:03d}/X_test_{:03d}_{:03d}.npy'.format(IN_LO, IN_HI, IN_LO, IN_HI))
+y_test = np.load('{:03d}_{:03d}/y_test_{:03d}_{:03d}.npy'.format(IN_LO, IN_HI, IN_LO, IN_HI))
+
+assert(X_train.shape[1] == IN_HI*2)
+assert(X_test.shape[1] == IN_HI*2)
+
+print('X_train', X_train.shape)
+print('y_train', y_train.shape)
+print('X_test', X_test.shape)
+print('y_test', y_test.shape)
+
+
+X_train_slice_lo = OU_LO*2
+X_train_slice_hi = OU_HI*2
+X_train_sliced = X_train[:,X_train_slice_lo:X_train_slice_hi]
+
+X_test_slice_lo = OU_LO*2
+X_test_slice_hi = OU_HI*2
+X_test_sliced = X_test[:,X_test_slice_lo:X_test_slice_hi]
+
+print('X_train (sliced)', X_train_sliced.shape)
+print('X_test (sliced)', X_test_sliced.shape)
+
+os.makedirs('{:03d}_{:03d}'.format(OU_LO, OU_HI), exist_ok=True)
+
+np.save('{:03d}_{:03d}/X_train_{:03d}_{:03d}.npy'.format(OU_LO, OU_HI, OU_LO, OU_HI), X_train_sliced)
+np.save('{:03d}_{:03d}/y_train_{:03d}_{:03d}.npy'.format(OU_LO, OU_HI, OU_LO, OU_HI), y_train)
+
+np.save('{:03d}_{:03d}/X_test_{:03d}_{:03d}.npy'.format(OU_LO, OU_HI, OU_LO, OU_HI), X_test_sliced)
+np.save('{:03d}_{:03d}/y_test_{:03d}_{:03d}.npy'.format(OU_LO, OU_HI, OU_LO, OU_HI), y_test)
+

data/qick_data/runme_0_50_350.sh

@@ -0,0 +1,4 @@
+for l in $(seq 0 50 350); do
+    h=$(($l + 400))
+    python generate_window.py --ou_lo $l --ou_hi $h
+done

hls_models/TEMPLATE_hls4ml_prj/.gitignore

@@ -0,0 +1 @@
+NN_prj

hls_models/TEMPLATE_hls4ml_prj/Makefile

@@ -0,0 +1,37 @@
+# Assuming this repo as a submodule of the qick repo
+# qick/submodules/ml-quantum-readout
+QICK_BASE_DIR = ../../../../
+
+help:
+	@echo "INFO: make <TAB> for targets"
+.PHONY: help
+
+hls:
+	@vim firmware/NN_axi.cpp +16
+	vivado_hls -f build_prj.tcl
+	@./profile.sh NN_prj/solution1/syn/report/NN_axi_csynth.xml NN_prj/solution1/impl/report/verilog/NN_axi_export.xml > xilinx_com_hls_NN_axi_1_0.log
+.PHONY: hls
+
+patch:
+	cp patch.sh NN_prj/solution1/impl/ip && cd NN_prj/solution1/impl/ip && ./patch.sh
+.PHONY: patch
+
+update-ip: ultraclean hls patch
+	@echo "WARNING: You need to manually copy the IP zip file"
+	@echo "WARNING: Match the right name on the target directory"
+	@vim firmware/NN_axi.cpp +16
+	@echo "WARNING: cp NN_prj/solution1/impl/ip/xilinx_com_hls_NN_axi_1_0.zip ${QICK_BASE_DIR}/qick_ml/ip/xilinx_com_hls_NN_axi_1_0_<CHANGE_HERE>_<FROM>_<TO>.zip"
+	@echo "WARNING: cp xilinx_com_hls_NN_axi_1_0.log ${QICK_BASE_DIR}/qick_ml/ip/xilinx_com_hls_NN_axi_1_0_<CHANGE_HERE>_<FROM>_<TO>.log"
+.PHONY: update-ip
+
+gui:
+	vivado_hls -p NN_prj
+.PHONY: gui
+
+clean:
+	@echo "INFO: make ultraclean"
+.PHONY: clean
+
+ultraclean:
+	rm -rf .Xil .hbs *log *rpt *jou NN*_prj tb_data/csim_results.log
+.PHONY: ultraclean

hls_models/TEMPLATE_hls4ml_prj/build_prj.tcl

@@ -0,0 +1,251 @@
+#################
+#    HLS4ML
+#################
+array set opt {
+    reset      0
+    csim       0
+    synth      1
+    cosim      0
+    validation 0
+    export     1
+    vsynth     0
+    fifo_opt   0
+}
+
+set tcldir [file dirname [info script]]
+source [file join $tcldir project.tcl]
+
+proc remove_recursive_log_wave {} {
+    set tcldir [file dirname [info script]]
+    source [file join $tcldir project.tcl]
+
+    set filename ${project_name}_prj/solution1/sim/verilog/${project_name}_axi.tcl
+    set timestamp [clock format [clock seconds] -format {%Y%m%d%H%M%S}]
+    set temp     $filename.new.$timestamp
+    # set backup   $filename.bak.$timestamp
+
+    set in  [open $filename r]
+    set out [open $temp     w]
+
+    # line-by-line, read the original file
+    while {[gets $in line] != -1} {
+        if {[string equal "$line" "log_wave -r /"]} {
+            set line { }
+        }
+        puts $out $line
+    }
+
+    close $in
+    close $out
+
+    # move the new data to the proper filename
+    file delete -force $filename
+    file rename -force $temp $filename
+}
+
+proc add_vcd_instructions_tcl {} {
+    set tcldir [file dirname [info script]]
+    source [file join $tcldir project.tcl]
+
+    set filename ${project_name}_prj/solution1/sim/verilog/${project_name}_axi.tcl
+    set timestamp [clock format [clock seconds] -format {%Y%m%d%H%M%S}]
+    set temp     $filename.new.$timestamp
+    # set backup   $filename.bak.$timestamp
+
+    set in  [open $filename r]
+    set out [open $temp     w]
+
+    # line-by-line, read the original file
+    while {[gets $in line] != -1} {
+        if {[string equal "$line" "log_wave -r /"]} {
+            set line {source "../../../../project.tcl"
+                if {[string equal "$backend" "vivadoaccelerator"]} {
+                    current_scope [get_scopes -regex "/apatb_${project_name}_axi_top/AESL_inst_${project_name}_axi/${project_name}_U0.*"]
+                    set scopes [get_scopes -regexp {layer(\d*)_.*data_0_V_U.*}]
+                    append scopes { }
+                    current_scope "/apatb_${project_name}_axi_top/AESL_inst_${project_name}_axi"
+                    append scopes [get_scopes -regexp {(in_local_V_data.*_0_.*)}]
+                    append scopes { }
+                    append scopes [get_scopes -regexp {(out_local_V_data.*_0_.*)}]
+                } else {
+                    current_scope [get_scopes -regex "/apatb_${project_name}_top/AESL_inst_${project_name}"]
+                    set scopes [get_scopes -regexp {layer(\d*)_.*data_0_V_U.*}]
+                }
+                open_vcd fifo_opt.vcd
+                foreach scope $scopes {
+                    current_scope $scope
+                    if {[catch [get_objects usedw]] == 0} {
+                        puts "$scope skipped"
+                        continue
+                    }
+                    set usedw [get_objects usedw]
+                    set depth [get_objects DEPTH]
+                    add_wave $usedw
+                    log_vcd $usedw
+                    log_wave $usedw
+                    add_wave $depth
+                    log_vcd $depth
+                    log_wave $depth
+                }
+            }
+        }
+
+        if {[string equal "$line" "quit"]} {
+            set line {flush_vcd
+                close_vcd
+                quit
+            }
+        }
+        # then write the transformed line
+        puts $out $line
+    }
+
+    close $in
+    close $out
+
+    # move the new data to the proper filename
+    file delete -force $filename
+    file rename -force $temp $filename
+}
+
+foreach arg $::argv {
+    foreach o [lsort [array names opt]] {
+        regexp "$o=+(\\w+)" $arg unused opt($o)
+    }
+}
+
+proc report_time { op_name time_start time_end } {
+    set time_taken [expr $time_end - $time_start]
+    set time_s [expr ($time_taken / 1000) % 60]
+    set time_m [expr ($time_taken / (1000*60)) % 60]
+    set time_h [expr ($time_taken / (1000*60*60)) % 24]
+    puts "***** ${op_name} COMPLETED IN ${time_h}h${time_m}m${time_s}s *****"
+}
+
+# Compare file content: 1 = same, 0 = different
+proc compare_files {file_1 file_2} {
+    # Check if files exist, error otherwise
+    if {! ([file exists $file_1] && [file exists $file_2])} {
+        return 0
+    }
+    # Files with different sizes are obviously different
+    if {[file size $file_1] != [file size $file_2]} {
+        return 0
+    }
+
+    # String compare the content of the files
+    set fh_1 [open $file_1 r]
+    set fh_2 [open $file_2 r]
+    set equal [string equal [read $fh_1] [read $fh_2]]
+    close $fh_1
+    close $fh_2
+    return $equal
+}
+
+file mkdir tb_data
+set CSIM_RESULTS "./tb_data/csim_results.log"
+set RTL_COSIM_RESULTS "./tb_data/rtl_cosim_results.log"
+
+if {$opt(reset)} {
+    open_project -reset ${project_name}_prj
+} else {
+    open_project ${project_name}_prj
+}
+set_top ${project_name}_axi
+add_files firmware/${project_name}_axi.cpp -cflags "-std=c++0x"
+add_files firmware/${project_name}.cpp -cflags "-std=c++0x"
+add_files -tb ${project_name}_test.cpp -cflags "-std=c++0x"
+add_files -tb firmware/weights
+add_files -tb tb_data
+if {$opt(reset)} {
+    open_solution -reset "solution1"
+} else {
+    open_solution "solution1"
+}
+catch {config_array_partition -maximum_size 4096}
+config_compile -name_max_length 80
+set_part $part
+config_schedule -enable_dsp_full_reg=false
+create_clock -period $clock_period -name default
+set_clock_uncertainty $clock_uncertainty default
+
+
+if {$opt(csim)} {
+    puts "***** C SIMULATION *****"
+    set time_start [clock clicks -milliseconds]
+    csim_design
+    set time_end [clock clicks -milliseconds]
+    report_time "C SIMULATION" $time_start $time_end
+}
+
+if {$opt(synth)} {
+    puts "***** C/RTL SYNTHESIS *****"
+    set time_start [clock clicks -milliseconds]
+    csynth_design
+    set time_end [clock clicks -milliseconds]
+    report_time "C/RTL SYNTHESIS" $time_start $time_end
+}
+
+if {$opt(cosim)} {
+    puts "***** C/RTL SIMULATION *****"
+    # TODO: This is a workaround (Xilinx defines __RTL_SIMULATION__ only for SystemC testbenches).
+    add_files -tb ${project_name}_test.cpp -cflags "-std=c++0x -DRTL_SIM"
+    set time_start [clock clicks -milliseconds]
+
+    cosim_design -trace_level all -setup
+
+    if {$opt(fifo_opt)} {
+        puts "\[hls4ml\] - FIFO optimization started"
+        add_vcd_instructions_tcl
+    }
+
+    remove_recursive_log_wave
+    set old_pwd [pwd]
+    cd ${project_name}_prj/solution1/sim/verilog/
+    source run_sim.tcl
+    cd $old_pwd
+
+    set time_end [clock clicks -milliseconds]
+    puts "INFO:"
+    if {[string equal "$backend" "vivadoaccelerator"]} {
+        puts [read [open ${project_name}_prj/solution1/sim/report/${project_name}_axi_cosim.rpt r]]
+    } else {
+        puts [read [open ${project_name}_prj/solution1/sim/report/${project_name}_cosim.rpt r]]
+    }
+    report_time "C/RTL SIMULATION" $time_start $time_end
+}
+
+if {$opt(validation)} {
+    puts "***** C/RTL VALIDATION *****"
+    if {[compare_files $CSIM_RESULTS $RTL_COSIM_RESULTS]} {
+        puts "INFO: Test PASSED"
+    } else {
+        puts "ERROR: Test failed"
+        puts "ERROR: - csim log:      $CSIM_RESULTS"
+        puts "ERROR: - RTL-cosim log: $RTL_COSIM_RESULTS"
+        exit 1
+    }
+}
+
+if {$opt(export)} {
+    puts "***** EXPORT IP *****"
+    set time_start [clock clicks -milliseconds]
+    export_design -format ip_catalog -rtl verilog -flow syn
+    set time_end [clock clicks -milliseconds]
+    report_time "EXPORT IP" $time_start $time_end
+}
+
+if {$opt(vsynth)} {
+    puts "***** VIVADO SYNTHESIS *****"
+    if {[file exist ${project_name}_prj/solution1/syn/vhdl]} {
+        set time_start [clock clicks -milliseconds]
+        exec vivado -mode batch -source vivado_synth.tcl >@ stdout
+        set time_end [clock clicks -milliseconds]
+        report_time "VIVADO SYNTHESIS" $time_start $time_end
+    } else {
+        puts "ERROR: Cannot find generated VHDL files. Did you run C synthesis?"
+        exit 1
+    }
+}
+
+exit