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Revert instructions where encoding is unrecognized
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@mininny
mininny committed Jan 13, 2025
1 parent bf4e465 commit b63defc
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Showing 4 changed files with 61 additions and 0 deletions.
24 changes: 24 additions & 0 deletions rvgo/fast/vm.go
View file
Original file line number Diff line number Diff line change
Expand Up @@ -660,11 +660,15 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
rdValue = shr64(and64(imm, toU64(0x3F)), rs1Value) // lower 6 bits in 64 bit mode
case 0x10: // 010000 = SRAI
rdValue = sar64(and64(imm, toU64(0x3F)), rs1Value) // lower 6 bits in 64 bit mode
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid imm value %d for opcode 0x13", imm))
}
case 6: // 110 = ORI
rdValue = or64(rs1Value, imm)
case 7: // 111 = ANDI
rdValue = and64(rs1Value, imm)
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x13", funct3))
}
setRegister(rd, rdValue)
setPC(add64(pc, toU64(4)))
Expand All @@ -684,7 +688,11 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
rdValue = signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), toU64(31))
case 0x20: // 0100000 = SRAIW
rdValue = signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), sub64(toU64(31), shamt))
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid imm value %d for opcode 0x1B", imm))
}
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x1B", funct3))
}
setRegister(rd, rdValue)
setPC(add64(pc, toU64(4)))
Expand Down Expand Up @@ -731,6 +739,8 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
default:
rdValue = mod64(rs1Value, rs2Value)
}
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x33", funct3))
}
default:
switch funct3 {
Expand All @@ -740,6 +750,8 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
rdValue = add64(rs1Value, rs2Value)
case 0x20: // 0100000 = SUB
rdValue = sub64(rs1Value, rs2Value)
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct7 value %d for funct3 %d", funct7, funct3))
}
case 1: // 001 = SLL
rdValue = shl64(and64(rs2Value, toU64(0x3F)), rs1Value) // only the low 6 bits are consider in RV6VI
Expand All @@ -755,11 +767,15 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
rdValue = shr64(and64(rs2Value, toU64(0x3F)), rs1Value) // logical: fill with zeroes
case 0x20: // 0100000 = SRA
rdValue = sar64(and64(rs2Value, toU64(0x3F)), rs1Value) // arithmetic: sign bit is extended
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct7 value %d for funct3 %d", funct7, funct3))
}
case 6: // 110 = OR
rdValue = or64(rs1Value, rs2Value)
case 7: // 111 = AND
rdValue = and64(rs1Value, rs2Value)
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x3B", funct3))
}
}
setRegister(rd, rdValue)
Expand Down Expand Up @@ -801,6 +817,8 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
default:
rdValue = mask32Signed64(mod64(and64(rs1Value, u32Mask()), and64(rs2Value, u32Mask())))
}
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x3B", funct3))
}
default:
switch funct3 {
Expand All @@ -810,6 +828,8 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
rdValue = mask32Signed64(add64(and64(rs1Value, u32Mask()), and64(rs2Value, u32Mask())))
case 0x20: // 0100000 = SUBW
rdValue = mask32Signed64(sub64(and64(rs1Value, u32Mask()), and64(rs2Value, u32Mask())))
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct7 value %d for funct3 %d", funct7, funct3))
}
case 1: // 001 = SLLW
rdValue = mask32Signed64(shl64(and64(rs2Value, toU64(0x1F)), rs1Value))
Expand All @@ -820,7 +840,11 @@ func (inst *InstrumentedState) riscvStep() (outErr error) {
rdValue = signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), toU64(31))
case 0x20: // 0100000 = SRAW
rdValue = signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), sub64(toU64(31), shamt))
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct7 value %d for funct3 %d", funct7, funct3))
}
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x3B", funct3))
}
}
setRegister(rd, rdValue)
Expand Down
1 change: 1 addition & 0 deletions rvgo/riscv/constants.go
View file
Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,7 @@ const (
ErrUnexpectedRProofLoad = uint64(0xbad22220)
ErrUnexpectedRProofStoreUnaligned = uint64(0xbad22221)
ErrUnexpectedRProofStore = uint64(0xbad2222f)
ErrIllegalInstruction = uint64(0xbadc0de)
ErrBadAMOSize = uint64(0xbada70)
ErrFailToReadPreimage = uint64(0xbadf00d0)
ErrBadMemoryProof = uint64(0xbadf00d1)
Expand Down
24 changes: 24 additions & 0 deletions rvgo/slow/vm.go
View file
Original file line number Diff line number Diff line change
Expand Up @@ -844,11 +844,15 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
rdValue = shr64(and64(imm, toU64(0x3F)), rs1Value) // lower 6 bits in 64 bit mode
case 0x10: // 010000 = SRAI
rdValue = sar64(and64(imm, toU64(0x3F)), rs1Value) // lower 6 bits in 64 bit mode
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid imm value %d for opcode 0x13", imm.val()))
}
case 6: // 110 = ORI
rdValue = or64(rs1Value, imm)
case 7: // 111 = ANDI
rdValue = and64(rs1Value, imm)
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x13", funct3.val()))
}
setRegister(rd, rdValue)
setPC(add64(pc, toU64(4)))
Expand All @@ -868,7 +872,11 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
rdValue = signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), toU64(31))
case 0x20: // 0100000 = SRAIW
rdValue = signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), sub64(toU64(31), shamt))
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid imm value %d for opcode 0x1B", imm.val()))
}
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x1B", funct3.val()))
}
setRegister(rd, rdValue)
setPC(add64(pc, toU64(4)))
Expand Down Expand Up @@ -915,6 +923,8 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
default:
rdValue = mod64(rs1Value, rs2Value)
}
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x33", funct3.val()))
}
default:
switch funct3.val() {
Expand All @@ -924,6 +934,8 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
rdValue = add64(rs1Value, rs2Value)
case 0x20: // 0100000 = SUB
rdValue = sub64(rs1Value, rs2Value)
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct7 value %d for funct3 %d", funct7.val(), funct3.val()))
}
case 1: // 001 = SLL
rdValue = shl64(and64(rs2Value, toU64(0x3F)), rs1Value) // only the low 6 bits are consider in RV6VI
Expand All @@ -939,11 +951,15 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
rdValue = shr64(and64(rs2Value, toU64(0x3F)), rs1Value) // logical: fill with zeroes
case 0x20: // 0100000 = SRA
rdValue = sar64(and64(rs2Value, toU64(0x3F)), rs1Value) // arithmetic: sign bit is extended
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct7 value %d for funct3 %d", funct7.val(), funct3.val()))
}
case 6: // 110 = OR
rdValue = or64(rs1Value, rs2Value)
case 7: // 111 = AND
rdValue = and64(rs1Value, rs2Value)
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x3B", funct3.val()))
}
}
setRegister(rd, rdValue)
Expand Down Expand Up @@ -985,6 +1001,8 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
default:
rdValue = mask32Signed64(mod64(and64(rs1Value, u32Mask()), and64(rs2Value, u32Mask())))
}
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x3B", funct3.val()))
}
default:
switch funct3.val() {
Expand All @@ -994,6 +1012,8 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
rdValue = mask32Signed64(add64(and64(rs1Value, u32Mask()), and64(rs2Value, u32Mask())))
case 0x20: // 0100000 = SUBW
rdValue = mask32Signed64(sub64(and64(rs1Value, u32Mask()), and64(rs2Value, u32Mask())))
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct7 value %d for funct3 %d", funct7.val(), funct3.val()))
}
case 1: // 001 = SLLW
rdValue = mask32Signed64(shl64(and64(rs2Value, toU64(0x1F)), rs1Value))
Expand All @@ -1004,7 +1024,11 @@ func Step(calldata []byte, po PreimageOracle) (stateHash common.Hash, outErr err
rdValue = signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), toU64(31))
case 0x20: // 0100000 = SRAW
rdValue = signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), sub64(toU64(31), shamt))
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct7 value %d for funct3 %d", funct7.val(), funct3.val()))
}
default:
revertWithCode(riscv.ErrIllegalInstruction, fmt.Errorf("illegal instruction: invalid funct3 value %d for opcode 0x3B", funct3.val()))
}
}
setRegister(rd, rdValue)
Expand Down
12 changes: 12 additions & 0 deletions rvsol/src/RISCV.sol
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1253,6 +1253,7 @@ contract RISCV is IBigStepper {
// 010000 = SRAI
rdValue := sar64(and64(imm, toU64(0x3F)), rs1Value) // lower 6 bits in 64 bit mode
}
default { revertWithCode(0xbadc0de) }
}
case 6 {
// 110 = ORI
Expand All @@ -1262,6 +1263,7 @@ contract RISCV is IBigStepper {
// 111 = ANDI
rdValue := and64(rs1Value, imm)
}
default { revertWithCode(0xbadc0de) }
setRegister(rd, rdValue)
setPC(add64(_pc, toU64(4)))
}
Expand Down Expand Up @@ -1292,7 +1294,9 @@ contract RISCV is IBigStepper {
// 0100000 = SRAIW
rdValue := signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), sub64(toU64(31), shamt))
}
default { revertWithCode(0xbadc0de) }
}
default { revertWithCode(0xbadc0de) }
setRegister(rd, rdValue)
setPC(add64(_pc, toU64(4)))
}
Expand Down Expand Up @@ -1346,6 +1350,7 @@ contract RISCV is IBigStepper {
case 0 { rdValue := rs1Value }
default { rdValue := mod64(rs1Value, rs2Value) }
}
default { revertWithCode(0xbadc0de) }
}
default {
switch funct3
Expand All @@ -1360,6 +1365,7 @@ contract RISCV is IBigStepper {
// 0100000 = SUB
rdValue := sub64(rs1Value, rs2Value)
}
default { revertWithCode(0xbadc0de) }
}
case 1 {
// 001 = SLL
Expand Down Expand Up @@ -1389,6 +1395,7 @@ contract RISCV is IBigStepper {
// 0100000 = SRA
rdValue := sar64(and64(rs2Value, toU64(0x3F)), rs1Value) // arithmetic: sign bit is extended
}
default { revertWithCode(0xbadc0de) }
}
case 6 {
// 110 = OR
Expand All @@ -1398,6 +1405,7 @@ contract RISCV is IBigStepper {
// 111 = AND
rdValue := and64(rs1Value, rs2Value)
}
default { revertWithCode(0xbadc0de) }
}
setRegister(rd, rdValue)
setPC(add64(_pc, toU64(4)))
Expand Down Expand Up @@ -1447,6 +1455,7 @@ contract RISCV is IBigStepper {
rdValue := mask32Signed64(mod64(and64(rs1Value, u32Mask()), and64(rs2Value, u32Mask())))
}
}
default { revertWithCode(0xbadc0de) }
}
default {
switch funct3
Expand All @@ -1461,6 +1470,7 @@ contract RISCV is IBigStepper {
// 0100000 = SUBW
rdValue := mask32Signed64(sub64(and64(rs1Value, u32Mask()), and64(rs2Value, u32Mask())))
}
default { revertWithCode(0xbadc0de) }
}
case 1 {
// 001 = SLLW
Expand All @@ -1478,7 +1488,9 @@ contract RISCV is IBigStepper {
// 0100000 = SRAW
rdValue := signExtend64(shr64(shamt, and64(rs1Value, u32Mask())), sub64(toU64(31), shamt))
}
default { revertWithCode(0xbadc0de) }
}
default { revertWithCode(0xbadc0de) }
}
setRegister(rd, rdValue)
setPC(add64(_pc, toU64(4)))
Expand Down

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