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[Feature Request]: Upload firmware via jtag. (VSC-427) #161

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ghost opened this issue Sep 9, 2020 · 4 comments · Fixed by #183
Closed

[Feature Request]: Upload firmware via jtag. (VSC-427) #161

ghost opened this issue Sep 9, 2020 · 4 comments · Fixed by #183
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Feature / Enhancement Request Request for Feature/ Enhancement ongoing Ongoing Issue or PR, this label will be used for issue or PR which is to be excluded by stale bot
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@ghost
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ghost commented Sep 9, 2020

I want to use your extension, but impossible upload firmware in my case.
My pcb has only jtag port.
No serial.....

Thank you!

@ghost ghost added the Feature / Enhancement Request Request for Feature/ Enhancement label Sep 9, 2020
@github-actions github-actions bot changed the title Upload firmware via jtag.[Feature Request]: Upload firmware via jtag.[Feature Request]: (VSC-427) Sep 9, 2020
@pwmb pwmb self-assigned this Sep 9, 2020
@pwmb
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pwmb commented Sep 9, 2020

Thanks for the feature request, we already have a plan in our roadmap to integrate jtag flashing directly from vscode, but this feature could take sometime to release.

Till then you can flash individual bins using openocd from terminal/cmd

$ openocd -f board/esp32-wrover-kit-3.3v.cfg -c "program_esp <app_name>.bin 0x10000 verify exit"

More info can be obtained here

@pwmb pwmb added the ongoing Ongoing Issue or PR, this label will be used for issue or PR which is to be excluded by stale bot label Sep 9, 2020
@pwmb pwmb added this to the Release Candidate v0.6.0 milestone Sep 9, 2020
@ghost
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ghost commented Sep 9, 2020

So, when approx will be released?

@pwmb
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pwmb commented Sep 10, 2020

This is planed to be released in v0.6.0, while we cannot comment on exact date because it's dependent on other projects like idf, openocd, etc.

We will keep you posted on this issue for any updates

@pwmb pwmb changed the title Upload firmware via jtag.[Feature Request]: (VSC-427) [Feature Request]: Upload firmware via jtag. (VSC-427) Sep 16, 2020
@pwmb pwmb mentioned this issue Sep 29, 2020
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@pwmb pwmb modified the milestones: Release Candidate v0.6.0, next Dec 9, 2020
@ToBoMi
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ToBoMi commented Dec 9, 2020

Till then you can flash individual bins using openocd from terminal/cmd

$ openocd -f board/esp32-wrover-kit-3.3v.cfg -c "program_esp <app_name>.bin 0x10000 verify exit"

More info can be obtained here

@pwmb: I tried this on the Adafruit HUZZAH32 without success.

I can flash this board using the serial cable but I cannot using JTAG.
I can debug this board with my JTAG connection - without problem. (The same command as below - without the -c option)

Here is the output:

C:\somepath>openocd -f ./esp-huzzah-32.cfg  -c "program_esp build/myapp.elf 0x10000 verify reset exit"
Open On-Chip Debugger  v0.10.0-esp32-20200709 (2020-07-09-08:54)
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
Info: esp-huzzah-32.cfg is not an official configuration file.
Info : Configured 2 cores
Info : J-Link V10 compiled Jul 23 2019 13:46:10
Info : Hardware version: 10.10
Info : VTarget = 3.321 V
Info : clock speed 14000 kHz
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : esp32: Debug controller 0 was reset.
Info : esp32: Core 0 was reset.
Info : esp32: Debug controller 1 was reset.
Info : esp32: Core 1 was reset.
Info : Listening on port 3333 for gdb connections
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : cpu0: Target halted, PC=0x40149F66, debug_reason=00000000
Info : cpu0: Debug controller 0 was reset.
Info : cpu0: Core 0 was reset.
Info : cpu0: Target halted, PC=0x500000CF, debug_reason=00000000
Info : esp32: Core 0 was reset.
Info : esp32: Debug controller 1 was reset.
Info : esp32: Core 1 was reset.
Info : Target halted. CPU0: PC=0x40000400 (active)
Info : Target halted. CPU1: PC=0x40000400
** Programming Started **
Info : cpu0: Target halted, PC=0x40091856, debug_reason=00000001
Info : Flash mapping 0: 0x10020 -> 0x3f400020, 120 KB
Info : Flash mapping 1: 0x30020 -> 0x400d0020, 492 KB
Info : cpu0: Target halted, PC=0x40091856, debug_reason=00000001
Info : Auto-detected flash bank 'esp32.flash' size 4096 KB
Info : Using flash bank 'esp32.flash' size 4096 KB
Info : cpu0: Target halted, PC=0x40091856, debug_reason=00000001
Info : Flash mapping 0: 0x10020 -> 0x3f400020, 120 KB
Info : Flash mapping 1: 0x30020 -> 0x400d0020, 492 KB
Info : Using flash bank 'esp32.irom' size 496 KB
Info : cpu0: Target halted, PC=0x40091856, debug_reason=00000001
Info : Flash mapping 0: 0x10020 -> 0x3f400020, 120 KB
Info : Flash mapping 1: 0x30020 -> 0x400d0020, 492 KB
Info : Using flash bank 'esp32.drom' size 124 KB
Warn : Adding extra erase range, 0x3f410000 .. 0x3f41001f
Info : cpu0: Target halted, PC=0x40091856, debug_reason=00000001
Info : cpu0: Target halted, PC=0x40091856, debug_reason=00000001
Warn : no flash bank found for address 0x3f41f000
Warn : no flash bank found for address 0x3ffcdb60
Warn : no flash bank found for address 0x40090000
Warn : Adding extra erase range, 0x400e0000 .. 0x400e001f
Info : cpu0: Target halted, PC=0x40091856, debug_reason=00000001
Info : cpu0: Target halted, PC=0x40091856, debug_reason=00000001
Warn : no flash bank found for address 0x4014c000
** Programming Finished **
** Verify Started **
Info : File content exceeds flash bank size. Only comparing the first 4128768 bytes of the file
Info : cpu0: Target halted, PC=0x40091856, debug_reason=00000001
** Verify Failed **
shutdown command invoked


C:\somepath>

How to work around this problem?
Let me know if this should become a separate issue.

edit : Follow up on this at espressif/openocd-esp32#128

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