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hw/ssi: update trans_done #40

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2a051f7
LOCAL: add CI jobs
igrr Sep 27, 2019
691089d
LOCAL: Revert "tcg: Optimize inline dup_const for MO_64"
igrr May 17, 2021
5989d57
xtensa: don't send window registers to GDB
igrr Jul 23, 2021
063fa05
LOCAL: target/xtensa: allow tweaking the list of registers sent to GDB
igrr Jul 25, 2021
1ab7c86
hw/block: correct DIO mode for Gigadevice SPI NOR flash
Apr 28, 2021
3de4e91
hw/net: opencores_eth: fix handling of DP83848C PHYSTS register
igrr Jun 4, 2021
4781849
target/xtensa: add stubs for "DFP Accelerator" instructions
igrr Aug 8, 2019
abca1ae
target/xtensa: add ESP32 core configuration
igrr Sep 27, 2019
ee700fa
hw/char: add ESP32 UART
igrr Sep 27, 2019
ed08d8c
hw/gpio: add ESP32 GPIO
igrr Sep 27, 2019
f1abba2
hw/nvram: add ESP32 eFuse
igrr Sep 27, 2019
22d66b3
hw/spi: add ESP32 SPI
igrr Sep 27, 2019
59b5d87
hw/i2c: add ESP32 I2C
peterus Sep 28, 2020
bd849dc
hw/misc: add ESP32 DPORT peripheral, cache, cross-core interrupt
igrr Sep 27, 2019
2771bfe
hw/misc: ESP32 RNG
igrr Sep 27, 2019
7a978f8
hw/misc: add ESP32 RSA
Aug 22, 2020
06362a0
hw/misc: ESP32 RTC controller
igrr Sep 27, 2019
5b9e357
hw/misc: add ESP32 SHA
igrr Sep 27, 2019
cfa367b
hw/misc: add ESP32 flash encryption module
igrr Feb 10, 2021
5c8b58e
hw/misc: add simple PSRAM emulation
igrr Jun 4, 2021
e4051d8
hw/timer: add ESP32 timers
igrr Sep 27, 2019
2a30a13
hw/sd: add emulation of designware sdmmc controller
igrr Jul 25, 2021
4cbe755
hw/misc: add ESP32 register base addresses
igrr Sep 27, 2019
5212ec7
hw/xtensa: add ESP32 interrupt matrix
igrr Jan 20, 2021
440ff71
hw/xtensa: add ESP32 machine
igrr Sep 27, 2019
7427ae3
hw/ssi: update trans_done
amirgon Apr 1, 2022
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LOCAL: target/xtensa: allow tweaking the list of registers sent to GDB
This commit introduces two environment variables which can be used
to adjust the list of registers sent from QEMU to GDB:
* If QEMU_XTENSA_CORE_REGS_ONLY is set, only non-privileged registers
  will be sent to GDB. This behavior is compatible with Espressif
  builds of GDB up to esp-2021r1.
* If QEMU_XTENSA_COUNT_WINDOW_REGS is set, QEMU will send window
  registers (a0-a15) to GDB. Enable this if you don't have a build of
  GDB which considers a0-a15 to be "raw" registers.
  • Loading branch information
igrr committed Dec 16, 2021
commit 063fa056a013c4412ed8fecefb59ae15cf36fdce
8 changes: 7 additions & 1 deletion target/xtensa/gdbstub.c
Original file line number Diff line number Diff line change
Expand Up @@ -46,11 +46,17 @@ void xtensa_count_regs(const XtensaConfig *config,
unsigned i;
bool count_core_regs = true;

/* Espressif local: allow changing the behavior here based on QEMU_XTENSA_COUNT_WINDOW_REGS
* environment variable.
*/
const char* count_window_regs_env = getenv("QEMU_XTENSA_COUNT_WINDOW_REGS");
bool count_window_regs = count_window_regs_env != NULL && strcmp(count_window_regs_env, "0") != 0;

for (i = 0; config->gdb_regmap.reg[i].targno >= 0; ++i) {
if (config->gdb_regmap.reg[i].type != xtRegisterTypeTieState &&
config->gdb_regmap.reg[i].type != xtRegisterTypeMapped &&
config->gdb_regmap.reg[i].type != xtRegisterTypeUnmapped &&
config->gdb_regmap.reg[i].type != xtRegisterTypeWindow) {
(config->gdb_regmap.reg[i].type != xtRegisterTypeWindow || count_window_regs)) {
++*n_regs;
if (count_core_regs) {
if ((config->gdb_regmap.reg[i].flags &
Expand Down
9 changes: 9 additions & 0 deletions target/xtensa/helper.c
Original file line number Diff line number Diff line change
Expand Up @@ -184,6 +184,15 @@ static void xtensa_core_class_init(ObjectClass *oc, void *data)
* in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
*/
cc->gdb_num_core_regs = config->gdb_regmap.num_regs;

/* Espressif local: allow changing the behavior here using
* QEMU_XTENSA_CORE_REGS_ONLY environment variable, to support different
* GDB builds
*/
const char* core_regs_only = getenv("QEMU_XTENSA_CORE_REGS_ONLY");
if (core_regs_only != NULL && strcmp(core_regs_only, "0") != 0) {
cc->gdb_num_core_regs = config->gdb_regmap.num_core_regs;
}
}

void xtensa_register_core(XtensaConfigList *node)
Expand Down