Change I2C Bus Reset to handle interrupted READ sequences. #2496
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The current code does not handle interrupted READ cycles. If a SLAVE device was in a read operation when the bus was interrupted, the SLAVE device is controlling SDA. The only bit during the 9 clock cycles of a byte READ the MASTER(ESP32) is guaranteed control over, is during the ACK bit period. If the SLAVE is sending a stream of ZERO bytes, it will only release SDA during the ACK bit period. The master(ESP32) cannot generate a STOP unless SDA is HIGH. So, this reset code synchronizes the bit stream with, Either, the ACK bit, Or a 1 bit.
I am stealing this delay coding from @jeremyherbert #2493 pr.
ryan-ma
reviewed
Oct 19, 2018
components/driver/i2c.c
Outdated
| gpio_set_level(scl_io, 0); | ||
| ets_delay_us(scl_half_period); | ||
| int i=0; | ||
| while( !gpio_get_level(sda_id) && (i<9)){ // cycle SCL until SDA is HIGH |
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Suggested change
| while( !gpio_get_level(sda_id) && (i<9)){ // cycle SCL until SDA is HIGH | |
| while( !gpio_get_level(sda_io) && (i<9)){ // cycle SCL until SDA is HIGH |
|
Yea, i my fault. I'll fix it. Chuck. |
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hi, |
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Thanks for contributing this fix, @stickbreaker . These commits have been cherry-picked with some other I2C fixes and should be merged to master shortly. |
igrr
pushed a commit
that referenced
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Jan 24, 2019
… SDA closes #2494 closes #2493 closes #2496 1. Change bus reset to handle interrupted READ sequences. 2. Slow down I2C to 100khz during reset 3. If a SLAVE device was in a read operation when the bus was interrupted, the SLAVE device is controlling SDA.The only bit during the 9 clock cycles of a byte READ the MASTER(ESP32) is guaranteed control over, is during the ACK bit period. If the SLAVE is sending a stream of ZERO bytes, it will only release SDA during the ACK bit period. The master(ESP32) cannot generate a STOP unless SDA is HIGH. So, this reset code synchronizes the bit stream with, Either, the ACK bit, Or a 1 bit.
igrr
pushed a commit
that referenced
this pull request
Jan 29, 2019
… SDA closes #2494 closes #2493 closes #2496 1. Change bus reset to handle interrupted READ sequences. 2. Slow down I2C to 100khz during reset 3. If a SLAVE device was in a read operation when the bus was interrupted, the SLAVE device is controlling SDA.The only bit during the 9 clock cycles of a byte READ the MASTER(ESP32) is guaranteed control over, is during the ACK bit period. If the SLAVE is sending a stream of ZERO bytes, it will only release SDA during the ACK bit period. The master(ESP32) cannot generate a STOP unless SDA is HIGH. So, this reset code synchronizes the bit stream with, Either, the ACK bit, Or a 1 bit.
catalinio
pushed a commit
to catalinio/pycom-esp-idf
that referenced
this pull request
Jun 28, 2019
… SDA closes espressif/esp-idf#2494 closes espressif/esp-idf#2493 closes espressif/esp-idf#2496 1. Change bus reset to handle interrupted READ sequences. 2. Slow down I2C to 100khz during reset 3. If a SLAVE device was in a read operation when the bus was interrupted, the SLAVE device is controlling SDA.The only bit during the 9 clock cycles of a byte READ the MASTER(ESP32) is guaranteed control over, is during the ACK bit period. If the SLAVE is sending a stream of ZERO bytes, it will only release SDA during the ACK bit period. The master(ESP32) cannot generate a STOP unless SDA is HIGH. So, this reset code synchronizes the bit stream with, Either, the ACK bit, Or a 1 bit.
catalinio
pushed a commit
to catalinio/pycom-esp-idf
that referenced
this pull request
Jun 28, 2019
… SDA closes espressif/esp-idf#2494 closes espressif/esp-idf#2493 closes espressif/esp-idf#2496 1. Change bus reset to handle interrupted READ sequences. 2. Slow down I2C to 100khz during reset 3. If a SLAVE device was in a read operation when the bus was interrupted, the SLAVE device is controlling SDA.The only bit during the 9 clock cycles of a byte READ the MASTER(ESP32) is guaranteed control over, is during the ACK bit period. If the SLAVE is sending a stream of ZERO bytes, it will only release SDA during the ACK bit period. The master(ESP32) cannot generate a STOP unless SDA is HIGH. So, this reset code synchronizes the bit stream with, Either, the ACK bit, Or a 1 bit.
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The current bus reset code does not handle interrupted READ cycles.
If a SLAVE device was in a READ operation when the bus was interrupted, the SLAVE device is controlling SDA.
The only bit during the 9 clock cycles of a byte READ the MASTER(ESP32) is guaranteed control over, is during the ACK bit period.
If the SLAVE is sending a stream of ZERO bytes, it will only release SDA during the ACK bit period. The master(ESP32) cannot generate a STOP unless SDA is HIGH.
So, this reset code synchronizes the bit stream with, Either, the ACK bit, Or a 1 bit.