Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

ESP32-S3 RTC slow memory data is lost when using USB Serial/JTAG Controller Console (IDFGH-7301) #8889

Closed
oursland opened this issue May 3, 2022 · 2 comments · Fixed by #8788
Closed

ESP32-S3 RTC slow memory data is lost when using USB Serial/JTAG Controller Console (IDFGH-7301) #8889

oursland opened this issue May 3, 2022 · 2 comments · Fixed by #8788
Labels
Resolution: Done Issue is done internally Status: Done Issue is done internally

Comments

@oursland
Copy link

oursland commented May 3, 2022

Environment

  • Development Kit: ESP32-S3-DevKitC-1
  • Kit version (for WroverKit/PicoKit/DevKitC): v1.6
  • Module or chip used: ESP32-S3-WROOM-1
  • IDF version (run git describe --tags to find it): v5.0-dev-2586-ga82e6e63d9
  • Build System: idf.py
  • Compiler version (run xtensa-esp32-elf-gcc --version to find it): xtensa-esp32-elf-gcc (crosstool-NG esp-2021r2-patch3) 8.4.0
  • Operating System: macOS
  • (Windows only) environment type:
  • Using an IDE?: VS Code with ESP-IDF extension
  • Power Supply: USB

Problem Description

Data stored in RTC slow memory is lost when waking from deep sleep if the USB Serial/JTAG Controller Console is attached.

The problem is caused by idf.py monitor ... resetting the chip on connect. On each boot, the USB-serial device appears and the monitor resets the device when opening the port.

The cause of the issue can be found in the following location serial_reader.py#L52. A command line switch to disable reset on connect would be beneficial in this use case.

Expected Behavior

The device should be able to wake from deep sleep when the USB Serial/JTAG Controller Console is used.

Actual Behavior

When the USB Serial/JTAG Controller Console is used to connect to the ESP32-S3, the device boots and quickly reboots (visible from the UART logs). The cause of this second reboot is USB_UART_CHIP_RESET.

Steps to reproduce

  1. Use the [deep_sleep}(https://github.com/espressif/esp-idf/tree/master/examples/system/deep_sleep) example program.
  2. Enable Ultra Low Power (ULP) Co-processor to enable RTC slow memory in sdkconfig (my sdkconfig.txt attached)
  3. Build, flash, and monitor via UART.
  4. Observe that the example behaves as expected.
  5. Attach an additional monitor using USB Serial/JTAG Controller Console.
  6. The device will now reboot a second time when the USB Serial/JTAG Controller Console.
  7. Observe that the RTC slow data does not persist.

wiring

Debug Logs

ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x5 (DSLEEP),boot:0x9 (SPI_FAST_FLASH_BOOT)
SPIWP:0xee
mode:DIO, clock div:1
load:0x3fcd0110,len:0x1994
load:0x403b6000,len:0xb70
load:0x403b9000,len:0x32f0
SHA-256 comparison failed:
Calculated: 05633df3cfed7e35f6216fc80e6de9b7480e6819c11147db89d41dda79068a41
Expected: a4c32ae149aec08b7be44eb2cdce4855d4c4bad81a55e9f806e88d2ee079188d
Attempting to boot anyway...
entry 0x403b6240
I (43) boot: ESP-IDF v5.0-dev-2586-ga82e6e63d9 2nd stage bootloader
I (43) boot: compile time 00:46:15
I (43) boot: chip revision: 0
I (47) boot.esp32s3: Boot SPI Speed : 80MHz
I (51) boot.esp32s3: SPI Mode       : DIO
I (56) boot.esp32s3: SPI Flash Size : 8MB
I (61) boot: Enabling RNG early entropy source...
I (66) esp_image: segment 0: paddr=00010020 vaddr=3c020020 size=083d0h ( 33744) map
I (74) esp_image: segment 1: paddr=000183f8 vaddr=3fc93400 size=03074h ( 12404) load
I (84) esp_image: segment 2: paddr=0001b474 vaddr=40374000 size=04ba4h ( 19364) load
I (93) esp_image: segment 3: paddr=00020020 vaddr=42000020 size=180c8h ( 98504) map
I (100) esp_image: segment 4: paddr=000380f0 vaddr=40378ba4 size=0a858h ( 43096) load
I (112) esp_image: segment 5: paddr=00042950 vaddr=600fe000 size=00044h (    68) 
I (116) boot: Fast booting app from partition at offset 0x10000
I (123) boot: Disabling RNG early entropy source...
I (140) opi psram: ECC is enabled
I (140) opi psram: vendor id    : 0x0d (AP)
I (140) opi psram: dev id       : 0x02 (generation 3)
I (143) opi psram: density      : 0x03 (64 Mbit)
I (148) opi psram: good-die     : 0x01 (Pass)
I (153) opi psram: Latency      : 0x01 (Fixed)
I (158) opi psram: VCC          : 0x01 (3V)
I (163) opi psram: SRF          : 0x01 (Fast Refresh)
I (169) opi psram: BurstType    : 0x00 ( Wrap)
I (174) opi psram: BurstLen     : 0x03 (1024 Byte)
I (180) opi psram: Readlatency  : 0x02 (10 cycles@Fixed)
I (186) opi psram: DriveStrength: 0x00 (1/1)
W (191) PSRAM: DO NOT USE FOR MASS PRODUCTION! Timing parameters will be updated in future IDF version.
I (201) spiram: Found 8MB SPI RAM device
I (205) spiram: Speed: 80MHz
I (645) spiram: SPI SRAM memory test OK
I (645) cpu_start: Pro cpu up.
I (650) cpu_start: Starting app cpu, entry point is 0x403753b0
0x403753b0: call_start_cpu1 at /Users/joursland/esp/esp-idf/components/esp_system/port/cpu_start.c:152

I (0) cpu_start: App cpu up.
I (664) cpu_start: Pro cpu start user code
I (664) cpu_start: cpu freq: 240000000 Hz
I (664) cpu_start: Application information:
I (667) cpu_start: Project name:     deESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x15 (USB_UART_CHIP_RESET),boot:0x9 (SPI_FAST_FLASH_BOOT)
Saved PC:0x40048836
SPIWP:0xee
mode:DIO, clock div:1
load:0x3fcd0110,len:0x1994
load:0x403b6000,len:0xb70
load:0x403b9000,len:0x32f0
SHA-256 comparison failed:
Calculated: 05633df3cfed7e35f6216fc80e6de9b7480e6819c11147db89d41dda79068a41
Expected: a4c32ae149aec08b7be44eb2cdce4855d4c4bad81a55e9f806e88d2ee079188d
Attempting to boot anyway...
entry 0x403b6240
I (43) boot: ESP-IDF v5.0-dev-2586-ga82e6e63d9 2nd stage bootloader
I (43) boot: compile time 00:46:15
I (43) boot: chip revision: 0
I (46) boot.esp32s3: Boot SPI Speed : 80MHz
I (51) boot.esp32s3: SPI Mode       : DIO
I (56) boot.esp32s3: SPI Flash Size : 8MB
I (61) boot: Enabling RNG early entropy source...
I (66) boot: Partition Table:
I (70) boot: ## Label            Usage          Type ST Offset   Length
I (77) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (84) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (92) boot:  2 factory          factory app      00 00 00010000 00100000
I (99) boot: End of partition table
I (103) esp_image: segment 0: paddr=00010020 vaddr=3c020020 size=083d0h ( 33744) map
I (118) esp_image: segment 1: paddr=000183f8 vaddr=3fc93400 size=03074h ( 12404) load
I (123) esp_image: segment 2: paddr=0001b474 vaddr=40374000 size=04ba4h ( 19364) load
I (133) esp_image: segment 3: paddr=00020020 vaddr=42000020 size=180c8h ( 98504) map
I (155) esp_image: segment 4: paddr=000380f0 vaddr=40378ba4 size=0a858h ( 43096) load
I (165) esp_image: segment 5: paddr=00042950 vaddr=600fe000 size=00044h (    68) load
I (171) boot: Loaded app from partition at offset 0x10000
I (172) boot: Disabling RNG early entropy source...
I (185) opi psram: ECC is enabled
I (185) opi psram: vendor id    : 0x0d (AP)
I (185) opi psram: dev id       : 0x02 (generation 3)
I (188) opi psram: density      : 0x03 (64 Mbit)
I (194) opi psram: good-die     : 0x01 (Pass)
I (199) opi psram: Latency      : 0x01 (Fixed)
I (204) opi psram: VCC          : 0x01 (3V)
I (209) opi psram: SRF          : 0x01 (Fast Refresh)
I (214) opi psram: BurstType    : 0x00 ( Wrap)
I (220) opi psram: BurstLen     : 0x03 (1024 Byte)
I (225) opi psram: Readlatency  : 0x02 (10 cycles@Fixed)
I (231) opi psram: DriveStrength: 0x00 (1/1)
W (236) PSRAM: DO NOT USE FOR MASS PRODUCTION! Timing parameters will be updated in future IDF version.
I (247) spiram: Found 8MB SPI RAM device
I (251) spiram: Speed: 80MHz
I (690) spiram: SPI SRAM memory test OK
I (691) cpu_start: Pro cpu up.
I (691) cpu_start: Starting app cpu, entry point is 0x403753b0
0x403753b0: call_start_cpu1 at /Users/joursland/esp/esp-idf/components/esp_system/port/cpu_start.c:152

I (0) cpu_start: App cpu up.
I (709) cpu_start: Pro cpu start user code
I (709) cpu_start: cpu freq: 240000000 Hz
I (709) cpu_start: Application information:
I (712) cpu_start: Project name:     deep_sleep
I (717) cpu_start: App version:      1
I (722) cpu_start: Compile time:     May  2 2022 00:46:23
I (728) cpu_start: ELF file SHA256:  0f7815164ac3cba6...
I (734) cpu_start: ESP-IDF:          v5.0-dev-2586-ga82e6e63d9
I (740) heap_init: Initializing. RAM available for dynamic allocation:
I (747) heap_init: At 3FC96EA0 len 00039160 (228 KiB): D/IRAM
I (754) heap_init: At 3FCD8000 len 00008000 (32 KiB): D/IRAM
I (760) heap_init: At 3FCE0000 len 0000EE34 (59 KiB): STACK/DRAM
I (767) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
I (773) spiram: Adding pool of 7680K of external SPI memory to heap allocator
I (781) spi_flash: detected chip: gd
I (785) spi_flash: flash io: dio
I (790) sleep: Configure to isolate all GPIO pins in sleep state
I (796) sleep: Enable automatic switching of GPIO sleep configuration
I (803) cpu_start: Starting scheduler on PRO CPU.
I (0) cpu_start: Starting scheduler on APP CPU.
I (823) spiram: Reserving pool of 32K of internal memory for DMA/internal allocations
Not a deep sleep reset
Enabling timer wakeup, 5s
Enabling EXT1 wakeup on pins GPIO2, GPIO4
Entering deep sleep
@espressif-bot espressif-bot added the Status: Opened Issue is new label May 3, 2022
@github-actions github-actions bot changed the title ESP32-S3 RTC slow memory data is lost when using USB Serial/JTAG Controller Console ESP32-S3 RTC slow memory data is lost when using USB Serial/JTAG Controller Console (IDFGH-7301) May 3, 2022
@dobairoland
Copy link
Collaborator

Hi @oursland. The requested feature is very close to be available: #8788

@dobairoland dobairoland linked a pull request May 5, 2022 that will close this issue
Add idf.py monitor argument --no-reset (-R) (IDFGH-7189) #8788
Merged
@FanhuaCloud
Copy link
Contributor

This should be the expected behavior and can be temporarily resolved with other serial debugging tools

@espressif-bot espressif-bot added Resolution: NA Issue resolution is unavailable Status: Done Issue is done internally Resolution: Done Issue is done internally and removed Status: Opened Issue is new Resolution: NA Issue resolution is unavailable labels May 10, 2022
espressif-bot pushed a commit that referenced this issue May 15, 2022
Tools: Add --no-reset option for IDF Monitor in order to avoid resett…
c02c0cc 
…ing the chip target upon connection

Closes #8889

Closes IDFGH-7189, IDFGH-7301, IDFGH-5963

Closes #7651

Merges #8788
espressif-bot pushed a commit to espressif/esp-idf-monitor that referenced this issue Jan 16, 2023
Tools: Add --no-reset option for IDF Monitor in order to avoid resett…
ffa2107 
…ing the chip target upon connection

Closes espressif/esp-idf#8889

Closes IDFGH-7189, IDFGH-7301, IDFGH-5963

Closes espressif/esp-idf#7651

Merges espressif/esp-idf#8788
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
Resolution: Done Issue is done internally Status: Done Issue is done internally
Projects
None yet
Milestone
No milestone
Development

Successfully merging a pull request may close this issue.

Add idf.py monitor argument --no-reset (-R) (IDFGH-7189) nonoo/esp-idf
4 participants
@oursland @dobairoland @FanhuaCloud @espressif-bot