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GPIO interrupts don't work if gpio_install_isr_service executes on APP cpu (IDFGH-5900) #7594

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KaeLL opened this issue Sep 23, 2021 · 8 comments
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Resolution: Done Issue is done internally Status: Done Issue is done internally

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@KaeLL
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KaeLL commented Sep 23, 2021

Environment

  • IDF version: v4.4-dev-3042-g220590d599

Problem Description

Title. Peripheral raises the GPIOs but the interrupt doesn't fire or isn't serviced. On the other hand, if everything but gpio_install_isr_service executes on APP cpu, it all works fine.
It's something related to running gpio_isr_register_on_core_static on the APP cpu.

@espressif-bot espressif-bot added the Status: Opened Issue is new label Sep 23, 2021
@github-actions github-actions bot changed the title GPIO interrupts don't work if gpio_install_isr_service executes on APP cpu GPIO interrupts don't work if gpio_install_isr_service executes on APP cpu (IDFGH-5900) Sep 23, 2021
@o-marshmallow o-marshmallow self-assigned this Oct 20, 2021
@pawel-soja
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I confirm that not all ports work on the second core.
Maybe it is related to the RTC (gpio 34, 35 ...)?

#include "driver/gpio.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"

#define GPIO_INT_CORE 1

static void IRAM_ATTR gpio_handler(void* arg)
{
    gpio_num_t pin_num = (gpio_num_t)(int)arg;
    ets_printf("gpio_handler; core: %d, pin: %d\n", xPortGetCoreID(), pin_num);
}

void gpio_initialize(void * arg)
{
    static int isr_initialized = 0;

    gpio_num_t pin_num = (gpio_num_t)(int)arg;

    gpio_config_t gpio_conf = {
        .pin_bit_mask=(1ULL << pin_num),
        .mode=GPIO_MODE_INPUT,
        .pull_up_en=GPIO_PULLUP_ENABLE,
        .pull_down_en=GPIO_PULLDOWN_DISABLE,
        .intr_type=GPIO_INTR_ANYEDGE,
    };
    ESP_ERROR_CHECK(gpio_config(&gpio_conf));

    if (!isr_initialized)
    {
        isr_initialized = 1;
        ESP_ERROR_CHECK(gpio_install_isr_service(0)); // only once
    }

    ESP_ERROR_CHECK(gpio_set_intr_type(pin_num, GPIO_INTR_ANYEDGE));
    ESP_ERROR_CHECK(gpio_isr_handler_add(pin_num, gpio_handler, (void*)pin_num));

    ets_printf("gpio_initialize; core: %d, pin: %d\n", xPortGetCoreID(), pin_num);

    for (;;)
        vTaskDelay(1000);
}

void app_main()
{
    vTaskDelay(100/portTICK_PERIOD_MS);
    xTaskCreatePinnedToCore(gpio_initialize, "gpio_initialize_19", 2048, (void *)(int)GPIO_NUM_19, 1, NULL, GPIO_INT_CORE);

    vTaskDelay(100/portTICK_PERIOD_MS);
    xTaskCreatePinnedToCore(gpio_initialize, "gpio_initialize_34", 2048, (void *)(int)GPIO_NUM_34, 1, NULL, GPIO_INT_CORE);

    for (;;)
        vTaskDelay(1000);
}

Core 0 - Works

I (0) cpu_start: Starting scheduler on APP CPU.
I (605) gpio: GPIO[19]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:3 
gpio_initialize; core: 0, pin: 19
I (705) gpio: GPIO[34]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:3 
gpio_initialize; core: 0, pin: 34
gpio_handler; core: 0, pin: 19
gpio_handler; core: 0, pin: 34
gpio_handler; core: 0, pin: 19

Core 1 - Bug

I (0) cpu_start: Starting scheduler on APP CPU.
I (100) gpio: GPIO[19]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:3 
gpio_initialize; core: 1, pin: 19
I (200) gpio: GPIO[34]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:3 
gpio_initialize; core: 1, pin: 34
gpio_handler; core: 1, pin: 19
gpio_handler; core: 1, pin: 19
gpio_handler; core: 1, pin: 19

Startup information:

I (28) boot: ESP-IDF v4.4-dev-3569-g6a7d83af19-dirty 2nd stage bootloader
I (29) boot: compile time 13:21:18
I (30) boot: chip revision: 1
I (33) boot_comm: chip revision: 1, min. bootloader chip revision: 0
I (41) boot.esp32: SPI Speed      : 40MHz
I (45) boot.esp32: SPI Mode       : DIO
I (50) boot.esp32: SPI Flash Size : 2MB
I (54) boot: Enabling RNG early entropy source...
I (60) boot: Partition Table:
I (63) boot: ## Label            Usage          Type ST Offset   Length
I (71) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (78) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (85) boot:  2 factory          factory app      00 00 00010000 00100000
I (93) boot: End of partition table
I (97) boot_comm: chip revision: 1, min. application chip revision: 0
I (104) esp_image: segment 0: paddr=00010020 vaddr=3f400020 size=19ecch (106188) map
I (151) esp_image: segment 1: paddr=00029ef4 vaddr=3ffb0000 size=02468h (  9320) load
I (155) esp_image: segment 2: paddr=0002c364 vaddr=40080000 size=03cb4h ( 15540) load
I (164) esp_image: segment 3: paddr=00030020 vaddr=400d0020 size=3f100h (258304) map
I (259) esp_image: segment 4: paddr=0006f128 vaddr=40083cb4 size=0772ch ( 30508) load
I (272) esp_image: segment 5: paddr=0007685c vaddr=50000000 size=00010h (    16) load
I (278) boot: Loaded app from partition at offset 0x10000
I (278) boot: Disabling RNG early entropy source...
I (292) cpu_start: Pro cpu up.
I (292) cpu_start: Starting app cpu, entry point is 0x40081170
0x40081170: call_start_cpu1 at /home/pawel/esp/idf/v4.4/components/esp_system/port/cpu_start.c:156

I (0) cpu_start: App cpu up.
I (306) cpu_start: Pro cpu start user code
I (306) cpu_start: cpu freq: 160000000
I (306) cpu_start: Application information:
I (311) cpu_start: Project name:     remote
I (316) cpu_start: App version:      b704caf
I (321) cpu_start: Compile time:     Nov  2 2021 13:21:07
I (327) cpu_start: ELF file SHA256:  359617a1d7c2a7b1...
I (333) cpu_start: ESP-IDF:          v4.4-dev-3569-g6a7d83af19-dirty
I (340) heap_init: Initializing. RAM available for dynamic allocation:
I (347) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
I (353) heap_init: At 3FFB43D8 len 0002BC28 (175 KiB): DRAM
I (359) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM
I (366) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (372) heap_init: At 4008B3E0 len 00014C20 (83 KiB): IRAM
I (379) spi_flash: detected chip: gd
I (383) spi_flash: flash io: dio
W (386) spi_flash: Detected size(16384k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
I (404) cpu_start: Starting scheduler on PRO CPU.

@chegewara
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Sorry for offtopic
@pawel-soja can i contact you somehow please?

@pawel-soja
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Sorry for offtopic @pawel-soja can i contact you somehow please?

Please see my github profile.

@pawel-soja
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Got it (acpu/pcpu)!

static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
{
*status = (core_id == 0) ? HAL_FORCE_READ_U32_REG_FIELD(hw->pcpu_int1, intr) : HAL_FORCE_READ_U32_REG_FIELD(hw->pcpu_int1, intr);
}

Should be:

*status = (core_id == 0) ? HAL_FORCE_READ_U32_REG_FIELD(hw->pcpu_int1, intr) : HAL_FORCE_READ_U32_REG_FIELD(hw->acpu_int1, intr);

@AxelLin
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AxelLin commented Nov 6, 2021

It was working in v4.3, this was broken by 874a720.

@nonoo
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nonoo commented Nov 8, 2021

I'm using ESP32-S3-DevKitC-1 v1.0 with the latest ESP-IDF (d0dd9ce) and by comparing the SOC gpio_struct.h header files between ESP32 and ESP32S3 (esp-idf/components/soc/esp32s3/include/soc/gpio_struct.h). It seems that the ESP32S3 does not have the acpu_int structure, so it can't receive GPIO interrupts on the app CPU.

Is this true?

I can't find any documentation about this, and the gpio_install_isr_service() and gpio_isr_handler_add() calls complete successfully, they don't give any warning about this.

@AxelLin
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AxelLin commented Nov 11, 2021

It was working in v4.3, this was broken by 874a720.

@o-marshmallow
Any follow up?

@o-marshmallow
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o-marshmallow commented Nov 11, 2021

Sorry for the delay,
Thanks @AxelLin for the commit that broke everything and @pawel-soja for finding the exact line!
This issue is currently being treated internally

@espressif-bot espressif-bot added Resolution: NA Issue resolution is unavailable Status: Done Issue is done internally Resolution: Done Issue is done internally and removed Status: Opened Issue is new Resolution: NA Issue resolution is unavailable labels Nov 11, 2021
espressif-bot pushed a commit that referenced this issue Nov 12, 2021
…re 1

Introduced in 874a720

Closes #7594

(cherry picked from commit 7ec38fc)
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