Merge branch 'feat/lp_core_lp_spi_support' into 'master'

feat(lp-spi): Added support for LP SPI to the LP core

Closes IDF-7538 and IDF-10210

See merge request espressif/esp-idf!31492

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -243,6 +243,10 @@ config SOC_LP_I2C_SUPPORTED
     bool
     default y
 
+config SOC_LP_SPI_SUPPORTED
+    bool
+    default y
+
 config SOC_SPIRAM_SUPPORTED
     bool
     default y
@@ -1279,6 +1283,14 @@ config SOC_SPI_MAX_PRE_DIVIDER
     int
     default 16
 
+config SOC_LP_SPI_PERIPH_NUM
+    bool
+    default y
+
+config SOC_LP_SPI_MAXIMUM_BUFFER_SIZE
+    int
+    default 64
+
 config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
     bool
     default y

components/soc/esp32p4/include/soc/lp_spi_struct.h

@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -116,7 +116,7 @@ typedef union {
         uint32_t reg_clkdiv_pre:4;
         uint32_t reserved_22:9;
         /** reg_clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
-         *  In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system
+         *  In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
          *  clock. Can be configured in CONF state.
          */
         uint32_t reg_clk_equ_sysclk:1;
@@ -813,244 +813,19 @@ typedef union {
 } lp_spi_sleep_conf1_reg_t;
 
 
-/** Group: LP SPI W0 REG */
-/** Type of spi_w0 register
- *  SPI CPU-controlled buffer0
+/** Group: LP SPI Wn REG */
+/** Type of spi_wn register
+ *  SPI CPU-controlled buffer
  */
 typedef union {
     struct {
-        /** reg_buf0 : R/W/SS; bitpos: [31:0]; default: 0;
+        /** reg_buf : R/W/SS; bitpos: [31:0]; default: 0;
          *  data buffer
          */
-        uint32_t reg_buf0:32;
+        uint32_t reg_buf:32;
     };
     uint32_t val;
-} lp_spi_w0_reg_t;
-
-
-/** Group: LP SPI W1 REG */
-/** Type of spi_w1 register
- *  SPI CPU-controlled buffer1
- */
-typedef union {
-    struct {
-        /** reg_buf1 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t reg_buf1:32;
-    };
-    uint32_t val;
-} lp_spi_w1_reg_t;
-
-
-/** Group: LP SPI W2 REG */
-/** Type of spi_w2 register
- *  SPI CPU-controlled buffer2
- */
-typedef union {
-    struct {
-        /** reg_buf2 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t reg_buf2:32;
-    };
-    uint32_t val;
-} lp_spi_w2_reg_t;
-
-
-/** Group: LP SPI W3 REG */
-/** Type of spi_w3 register
- *  SPI CPU-controlled buffer3
- */
-typedef union {
-    struct {
-        /** reg_buf3 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t reg_buf3:32;
-    };
-    uint32_t val;
-} lp_spi_w3_reg_t;
-
-
-/** Group: LP SPI W4 REG */
-/** Type of spi_w4 register
- *  SPI CPU-controlled buffer4
- */
-typedef union {
-    struct {
-        /** reg_buf4 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t reg_buf4:32;
-    };
-    uint32_t val;
-} lp_spi_w4_reg_t;
-
-
-/** Group: LP SPI W5 REG */
-/** Type of spi_w5 register
- *  SPI CPU-controlled buffer5
- */
-typedef union {
-    struct {
-        /** reg_buf5 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t reg_buf5:32;
-    };
-    uint32_t val;
-} lp_spi_w5_reg_t;
-
-
-/** Group: LP SPI W6 REG */
-/** Type of spi_w6 register
- *  SPI CPU-controlled buffer6
- */
-typedef union {
-    struct {
-        /** reg_buf6 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t reg_buf6:32;
-    };
-    uint32_t val;
-} lp_spi_w6_reg_t;
-
-
-/** Group: LP SPI W7 REG */
-/** Type of spi_w7 register
- *  SPI CPU-controlled buffer7
- */
-typedef union {
-    struct {
-        /** reg_buf7 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t reg_buf7:32;
-    };
-    uint32_t val;
-} lp_spi_w7_reg_t;
-
-
-/** Group: LP SPI W8 REG */
-/** Type of spi_w8 register
- *  SPI CPU-controlled buffer8
- */
-typedef union {
-    struct {
-        /** reg_buf8 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t reg_buf8:32;
-    };
-    uint32_t val;
-} lp_spi_w8_reg_t;
-
-
-/** Group: LP SPI W9 REG */
-/** Type of spi_w9 register
- *  SPI CPU-controlled buffer9
- */
-typedef union {
-    struct {
-        /** reg_buf9 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t reg_buf9:32;
-    };
-    uint32_t val;
-} lp_spi_w9_reg_t;
-
-
-/** Group: LP SPI W10 REG */
-/** Type of spi_w10 register
- *  SPI CPU-controlled buffer10
- */
-typedef union {
-    struct {
-        /** reg_buf10 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t reg_buf10:32;
-    };
-    uint32_t val;
-} lp_spi_w10_reg_t;
-
-
-/** Group: LP SPI W11 REG */
-/** Type of spi_w11 register
- *  SPI CPU-controlled buffer11
- */
-typedef union {
-    struct {
-        /** reg_buf11 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t reg_buf11:32;
-    };
-    uint32_t val;
-} lp_spi_w11_reg_t;
-
-
-/** Group: LP SPI W12 REG */
-/** Type of spi_w12 register
- *  SPI CPU-controlled buffer12
- */
-typedef union {
-    struct {
-        /** reg_buf12 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t reg_buf12:32;
-    };
-    uint32_t val;
-} lp_spi_w12_reg_t;
-
-
-/** Group: LP SPI W13 REG */
-/** Type of spi_w13 register
- *  SPI CPU-controlled buffer13
- */
-typedef union {
-    struct {
-        /** reg_buf13 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t reg_buf13:32;
-    };
-    uint32_t val;
-} lp_spi_w13_reg_t;
-
-
-/** Group: LP SPI W14 REG */
-/** Type of spi_w14 register
- *  SPI CPU-controlled buffer14
- */
-typedef union {
-    struct {
-        /** reg_buf14 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t reg_buf14:32;
-    };
-    uint32_t val;
-} lp_spi_w14_reg_t;
-
-
-/** Group: LP SPI W15 REG */
-/** Type of spi_w15 register
- *  SPI CPU-controlled buffer15
- */
-typedef union {
-    struct {
-        /** reg_buf15 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t reg_buf15:32;
-    };
-    uint32_t val;
-} lp_spi_w15_reg_t;
+} lp_spi_wn_reg_t;
 
 
 /** Group: LP SPI SLAVE REG */
@@ -1062,7 +837,7 @@ typedef union {
         /** reg_clk_mode : R/W; bitpos: [1:0]; default: 0;
          *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
          *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
-         *  SPI clock is alwasy on. Can be configured in CONF state.
+         *  SPI clock is always on. Can be configured in CONF state.
          */
         uint32_t reg_clk_mode:2;
         /** reg_clk_mode_13 : R/W; bitpos: [2]; default: 0;
@@ -1238,22 +1013,7 @@ typedef struct {
     volatile lp_spi_sleep_conf1_reg_t spi_sleep_conf1;
     volatile lp_spi_dma_int_set_reg_t spi_dma_int_set;
     uint32_t reserved_050[18];
-    volatile lp_spi_w0_reg_t spi_w0;
-    volatile lp_spi_w1_reg_t spi_w1;
-    volatile lp_spi_w2_reg_t spi_w2;
-    volatile lp_spi_w3_reg_t spi_w3;
-    volatile lp_spi_w4_reg_t spi_w4;
-    volatile lp_spi_w5_reg_t spi_w5;
-    volatile lp_spi_w6_reg_t spi_w6;
-    volatile lp_spi_w7_reg_t spi_w7;
-    volatile lp_spi_w8_reg_t spi_w8;
-    volatile lp_spi_w9_reg_t spi_w9;
-    volatile lp_spi_w10_reg_t spi_w10;
-    volatile lp_spi_w11_reg_t spi_w11;
-    volatile lp_spi_w12_reg_t spi_w12;
-    volatile lp_spi_w13_reg_t spi_w13;
-    volatile lp_spi_w14_reg_t spi_w14;
-    volatile lp_spi_w15_reg_t spi_w15;
+    volatile lp_spi_wn_reg_t data_buf[16];
     uint32_t reserved_0d8[2];
     volatile lp_spi_slave_reg_t spi_slave;
     volatile lp_spi_slave1_reg_t spi_slave1;
@@ -1263,11 +1023,12 @@ typedef struct {
     volatile lp_rnd_eco_cs_reg_t rnd_eco_cs;
     volatile lp_rnd_eco_low_reg_t rnd_eco_low;
     volatile lp_rnd_eco_high_reg_t rnd_eco_high;
-} lp_dev_t;
+} lp_spi_dev_t;
 
+extern lp_spi_dev_t LP_SPI;
 
 #ifndef __cplusplus
-_Static_assert(sizeof(lp_dev_t) == 0x100, "Invalid size of lp_dev_t structure");
+_Static_assert(sizeof(lp_spi_dev_t) == 0x100, "Invalid size of lp_dev_t structure");
 #endif
 
 #ifdef __cplusplus

components/soc/esp32p4/include/soc/soc_caps.h

@@ -78,6 +78,7 @@
 #define SOC_LP_GPIO_MATRIX_SUPPORTED    1
 #define SOC_LP_PERIPHERALS_SUPPORTED    1
 #define SOC_LP_I2C_SUPPORTED            1
+#define SOC_LP_SPI_SUPPORTED            1
 #define SOC_SPIRAM_SUPPORTED            1
 #define SOC_PSRAM_DMA_CAPABLE           1
 // #define SOC_ULP_SUPPORTED               1  //TODO: IDF-7534
@@ -504,6 +505,10 @@
 #define SOC_MEMSPI_IS_INDEPENDENT   1
 #define SOC_SPI_MAX_PRE_DIVIDER     16
 
+/*-------------------------- LP SPI CAPS ----------------------------------------*/
+#define SOC_LP_SPI_PERIPH_NUM              1
+#define SOC_LP_SPI_MAXIMUM_BUFFER_SIZE     64
+
 /*-------------------------- SPI MEM CAPS ---------------------------------------*/
 #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE                (1)
 #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND                  (1)

components/ulp/CMakeLists.txt

@@ -65,6 +65,10 @@ if(CONFIG_ULP_COPROC_TYPE_LP_CORE)
     if(CONFIG_SOC_LP_TIMER_SUPPORTED)
         list(APPEND srcs "lp_core/shared/ulp_lp_core_lp_timer_shared.c")
     endif()
+
+    if(CONFIG_SOC_LP_SPI_SUPPORTED)
+        list(APPEND srcs "lp_core/lp_core_spi.c")
+    endif()
 endif()
 
 idf_component_register(SRCS ${srcs}

components/ulp/cmake/CMakeLists.txt

@@ -114,7 +114,8 @@ elseif(ULP_COCPU_IS_LP_CORE)
     "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_print.c"
     "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_panic.c"
     "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_interrupt.c"
-    "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_i2c.c")
+    "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_i2c.c"
+    "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_spi.c")
 
     target_link_options(${ULP_APP_NAME} PRIVATE "-nostartfiles")
     target_link_options(${ULP_APP_NAME} PRIVATE "-Wl,--no-warn-rwx-segments")