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Merge branch 'refactor/pll_pd_in_sleep_logic' into 'master'
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fix(clk): rtc_clk_cpu_freq_set_xtal will always disable CPU's PLL

See merge request espressif/esp-idf!34241
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@songruo
songruo committed Oct 18, 2024
2 parents 63cf6f9 + 7c0b1dc commit ed91ad5
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Showing 22 changed files with 58 additions and 204 deletions.
15 changes: 5 additions & 10 deletions components/esp_hw_support/include/esp_private/rtc_clk.h
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Original file line number Diff line number Diff line change
Expand Up @@ -18,11 +18,12 @@ extern "C" {
* @brief Switch CPU clock source to XTAL, and let cpu frequency equal to main XTAL frequency.
*
* This function does not disable CPU's source PLL. If the PLL requires to be disabled to save power, please call
* `rtc_clk_cpu_freq_set_xtal` instead. It does one extra check (if necessary) to see whether can disable the
* corresponding PLL after switching the CPU clock source to XTAL.
* `rtc_clk_cpu_freq_set_xtal` instead. It will always disable the corresponding PLL after switching the CPU clock
* source to XTAL (except for S2).
*
* Currently, this function should only be called in `esp_restart_noos` and `esp_restart_noos_dig` to switch the CPU
* clock source back to XTAL (by default) before reset.
* Currently, this function is only called in `esp_restart_noos` and `esp_restart_noos_dig` to switch the CPU
* clock source back to XTAL (by default) before reset, and in `esp_sleep_start` to switch CPU clock source to XTAL
* before entering sleep for PMU supported chips.
*/
void rtc_clk_cpu_set_to_default_config(void);

Expand All @@ -32,12 +33,6 @@ void rtc_clk_cpu_set_to_default_config(void);
* Currently, this function is only used for tracking whether USB Serial/JTAG is using the 48MHz PHY clock
*
* Note: Calling this function only helps to not disable the BBPLL clock in `rtc_clk_cpu_freq_set_config`.
* For light and deep sleep, whether to disable the BBPLL in the internal call to `rtc_clk_cpu_freq_set_xtal`
* varies for targets.
* On ESP32C3/S3, USB CDC device can not function properly during sleep due to the lack of APB clock. Therefore.
* `rtc_clk_cpu_freq_set_xtal` will always disable BBPLL, no matter whether BBPLL has any consumer.
* On ESP32C6/H2, USB CDC device can maintain the minimum connection with the host during sleep, so
* `rtc_clk_cpu_freq_set_xtal` will check for BBPLL consumers, and keep BBPLL if USB Serial/JTAG is in use.
*/
void rtc_clk_bbpll_add_consumer(void);

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5 changes: 3 additions & 2 deletions components/esp_hw_support/port/esp32c5/include/soc/rtc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -307,8 +307,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
* rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
* Assumes that XTAL frequency has been determined — don't call in startup code.
*
* @note On ESP32C5, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be
* turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL.
* @note This function always disables BBPLL after switching the CPU clock source to XTAL for power saving purpose.
* If this is unwanted, please use rtc_clk_cpu_freq_set_config. It helps to check whether USB Serial JTAG is in use,
* if so, then BBPLL will not be turned off.
*/
void rtc_clk_cpu_freq_set_xtal(void);

Expand Down
37 changes: 3 additions & 34 deletions components/esp_hw_support/port/esp32c5/pmu_param.c
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Original file line number Diff line number Diff line change
Expand Up @@ -291,18 +291,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
.hp_sleep2active_backup_en = 0, \
.hp_modem2active_backup_en = 0, \
}, \
.backup_clk = ( \
BIT(PMU_ICG_FUNC_ENA_REGDMA) | \
BIT(PMU_ICG_FUNC_ENA_GDMA) | \
BIT(PMU_ICG_FUNC_ENA_TG0) | \
BIT(PMU_ICG_FUNC_ENA_TG1) | \
BIT(PMU_ICG_FUNC_ENA_HPBUS) | \
BIT(PMU_ICG_FUNC_ENA_MSPI) | \
BIT(PMU_ICG_FUNC_ENA_IOMUX) | \
BIT(PMU_ICG_FUNC_ENA_SPI2) | \
BIT(PMU_ICG_FUNC_ENA_UART0) | \
BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \
) \
.backup_clk = 0xffffffff, \
}

#define PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT() { \
Expand All @@ -314,17 +303,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
.hp_sleep2modem_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 1), \
.hp_sleep2modem_backup_en = 0, \
}, \
.backup_clk = ( \
BIT(PMU_ICG_FUNC_ENA_REGDMA) | \
BIT(PMU_ICG_FUNC_ENA_TG0) | \
BIT(PMU_ICG_FUNC_ENA_TG1) | \
BIT(PMU_ICG_FUNC_ENA_HPBUS) | \
BIT(PMU_ICG_FUNC_ENA_MSPI) | \
BIT(PMU_ICG_FUNC_ENA_IOMUX) | \
BIT(PMU_ICG_FUNC_ENA_SPI2) | \
BIT(PMU_ICG_FUNC_ENA_UART0) | \
BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \
) \
.backup_clk = 0xffffffff, \
}

#define PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() { \
Expand All @@ -341,17 +320,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
.hp_modem2sleep_backup_en = 0, \
.hp_active2sleep_backup_en = 0, \
}, \
.backup_clk = ( \
BIT(PMU_ICG_FUNC_ENA_REGDMA) | \
BIT(PMU_ICG_FUNC_ENA_TG0) | \
BIT(PMU_ICG_FUNC_ENA_TG1) | \
BIT(PMU_ICG_FUNC_ENA_HPBUS) | \
BIT(PMU_ICG_FUNC_ENA_MSPI) | \
BIT(PMU_ICG_FUNC_ENA_IOMUX) | \
BIT(PMU_ICG_FUNC_ENA_SPI2) | \
BIT(PMU_ICG_FUNC_ENA_UART0) | \
BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \
) \
.backup_clk = 0xffffffff, \
}

const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode)
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2 changes: 1 addition & 1 deletion components/esp_hw_support/port/esp32c5/private_include/pmu_param.h
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Original file line number Diff line number Diff line change
Expand Up @@ -87,7 +87,7 @@ const pmu_hp_system_analog_param_t* pmu_hp_system_analog_param_default(pmu_hp_mo

typedef struct {
pmu_hp_backup_reg_t retention;
uint32_t backup_clk;
uint32_t backup_clk; // icg_func
} pmu_hp_system_retention_param_t;

const pmu_hp_system_retention_param_t* pmu_hp_system_retention_param_default(pmu_hp_mode_t mode);
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6 changes: 2 additions & 4 deletions components/esp_hw_support/port/esp32c5/rtc_clk.c
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Original file line number Diff line number Diff line change
Expand Up @@ -383,17 +383,15 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
void rtc_clk_cpu_freq_set_xtal(void)
{
rtc_clk_cpu_set_to_default_config();
// We don't turn off the bbpll if some consumers depend on bbpll
if (!s_bbpll_digi_consumers_ref_count) {
rtc_clk_bbpll_disable();
}
rtc_clk_bbpll_disable();
}

void rtc_clk_cpu_set_to_default_config(void)
{
int freq_mhz = (int)rtc_clk_xtal_freq_get();

rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep
}

void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
Expand Down
5 changes: 3 additions & 2 deletions components/esp_hw_support/port/esp32c6/include/soc/rtc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -338,8 +338,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
* rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
* Assumes that XTAL frequency has been determined — don't call in startup code.
*
* @note On ESP32C6, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be
* turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL.
* @note This function always disables BBPLL after switching the CPU clock source to XTAL for power saving purpose.
* If this is unwanted, please use rtc_clk_cpu_freq_set_config. It helps to check whether USB Serial JTAG is in use,
* if so, then BBPLL will not be turned off.
*/
void rtc_clk_cpu_freq_set_xtal(void);

Expand Down
38 changes: 3 additions & 35 deletions components/esp_hw_support/port/esp32c6/pmu_param.c
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Original file line number Diff line number Diff line change
Expand Up @@ -291,18 +291,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
.hp_sleep2active_backup_en = 0, \
.hp_modem2active_backup_en = 0, \
}, \
.backup_clk = ( \
BIT(PMU_ICG_FUNC_ENA_GDMA) | \
BIT(PMU_ICG_FUNC_ENA_REGDMA) | \
BIT(PMU_ICG_FUNC_ENA_TG0) | \
BIT(PMU_ICG_FUNC_ENA_TG1) | \
BIT(PMU_ICG_FUNC_ENA_HPBUS) | \
BIT(PMU_ICG_FUNC_ENA_MSPI) | \
BIT(PMU_ICG_FUNC_ENA_IOMUX) | \
BIT(PMU_ICG_FUNC_ENA_SPI2) | \
BIT(PMU_ICG_FUNC_ENA_UART0) | \
BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \
) \
.backup_clk = 0xffffffff, \
}

#define PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT() { \
Expand All @@ -314,17 +303,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
.hp_sleep2modem_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 1), \
.hp_sleep2modem_backup_en = 0, \
}, \
.backup_clk = ( \
BIT(PMU_ICG_FUNC_ENA_REGDMA) | \
BIT(PMU_ICG_FUNC_ENA_TG0) | \
BIT(PMU_ICG_FUNC_ENA_TG1) | \
BIT(PMU_ICG_FUNC_ENA_HPBUS) | \
BIT(PMU_ICG_FUNC_ENA_MSPI) | \
BIT(PMU_ICG_FUNC_ENA_IOMUX) | \
BIT(PMU_ICG_FUNC_ENA_SPI2) | \
BIT(PMU_ICG_FUNC_ENA_UART0) | \
BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \
) \
.backup_clk = 0xffffffff, \
}

#define PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() { \
Expand All @@ -341,18 +320,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
.hp_modem2sleep_backup_en = 0, \
.hp_active2sleep_backup_en = 0, \
}, \
.backup_clk = ( \
BIT(PMU_ICG_FUNC_ENA_GDMA) | \
BIT(PMU_ICG_FUNC_ENA_REGDMA) | \
BIT(PMU_ICG_FUNC_ENA_TG0) | \
BIT(PMU_ICG_FUNC_ENA_TG1) | \
BIT(PMU_ICG_FUNC_ENA_HPBUS) | \
BIT(PMU_ICG_FUNC_ENA_MSPI) | \
BIT(PMU_ICG_FUNC_ENA_IOMUX) | \
BIT(PMU_ICG_FUNC_ENA_SPI2) | \
BIT(PMU_ICG_FUNC_ENA_UART0) | \
BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \
) \
.backup_clk = 0xffffffff, \
}

const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode)
Expand Down
2 changes: 1 addition & 1 deletion components/esp_hw_support/port/esp32c6/private_include/pmu_param.h
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Original file line number Diff line number Diff line change
Expand Up @@ -92,7 +92,7 @@ const pmu_hp_system_analog_param_t* pmu_hp_system_analog_param_default(pmu_hp_mo

typedef struct {
pmu_hp_backup_reg_t retention;
uint32_t backup_clk;
uint32_t backup_clk; // icg_func
} pmu_hp_system_retention_param_t;

const pmu_hp_system_retention_param_t* pmu_hp_system_retention_param_default(pmu_hp_mode_t mode);
Expand Down
6 changes: 2 additions & 4 deletions components/esp_hw_support/port/esp32c6/rtc_clk.c
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Original file line number Diff line number Diff line change
Expand Up @@ -333,17 +333,15 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
void rtc_clk_cpu_freq_set_xtal(void)
{
rtc_clk_cpu_set_to_default_config();
// We don't turn off the bbpll if some consumers depend on bbpll
if (!s_bbpll_digi_consumers_ref_count) {
rtc_clk_bbpll_disable();
}
rtc_clk_bbpll_disable();
}

void rtc_clk_cpu_set_to_default_config(void)
{
int freq_mhz = (int)rtc_clk_xtal_freq_get();

rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep
}

void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
Expand Down
5 changes: 3 additions & 2 deletions components/esp_hw_support/port/esp32c61/include/soc/rtc.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -307,8 +307,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
* rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
* Assumes that XTAL frequency has been determined — don't call in startup code.
*
* @note On ESP32C61, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be
* turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL.
* @note This function always disables BBPLL after switching the CPU clock source to XTAL for power saving purpose.
* If this is unwanted, please use rtc_clk_cpu_freq_set_config. It helps to check whether USB Serial JTAG is in use,
* if so, then BBPLL will not be turned off.
*/
void rtc_clk_cpu_freq_set_xtal(void);

Expand Down
37 changes: 3 additions & 34 deletions components/esp_hw_support/port/esp32c61/pmu_param.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -290,18 +290,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
.hp_sleep2active_backup_en = 0, \
.hp_modem2active_backup_en = 0, \
}, \
.backup_clk = ( \
BIT(PMU_ICG_FUNC_ENA_REGDMA) | \
BIT(PMU_ICG_FUNC_ENA_GDMA) | \
BIT(PMU_ICG_FUNC_ENA_TG0) | \
BIT(PMU_ICG_FUNC_ENA_TG1) | \
BIT(PMU_ICG_FUNC_ENA_HPBUS) | \
BIT(PMU_ICG_FUNC_ENA_MSPI) | \
BIT(PMU_ICG_FUNC_ENA_IOMUX) | \
BIT(PMU_ICG_FUNC_ENA_SPI2) | \
BIT(PMU_ICG_FUNC_ENA_UART0) | \
BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \
) \
.backup_clk = 0xffffffff, \
}

#define PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT() { \
Expand All @@ -313,17 +302,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
.hp_sleep2modem_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 1), \
.hp_sleep2modem_backup_en = 0, \
}, \
.backup_clk = ( \
BIT(PMU_ICG_FUNC_ENA_REGDMA) | \
BIT(PMU_ICG_FUNC_ENA_TG0) | \
BIT(PMU_ICG_FUNC_ENA_TG1) | \
BIT(PMU_ICG_FUNC_ENA_HPBUS) | \
BIT(PMU_ICG_FUNC_ENA_MSPI) | \
BIT(PMU_ICG_FUNC_ENA_IOMUX) | \
BIT(PMU_ICG_FUNC_ENA_SPI2) | \
BIT(PMU_ICG_FUNC_ENA_UART0) | \
BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \
) \
.backup_clk = 0xffffffff, \
}

#define PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() { \
Expand All @@ -340,17 +319,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
.hp_modem2sleep_backup_en = 0, \
.hp_active2sleep_backup_en = 0, \
}, \
.backup_clk = ( \
BIT(PMU_ICG_FUNC_ENA_REGDMA) | \
BIT(PMU_ICG_FUNC_ENA_TG0) | \
BIT(PMU_ICG_FUNC_ENA_TG1) | \
BIT(PMU_ICG_FUNC_ENA_HPBUS) | \
BIT(PMU_ICG_FUNC_ENA_MSPI) | \
BIT(PMU_ICG_FUNC_ENA_IOMUX) | \
BIT(PMU_ICG_FUNC_ENA_SPI2) | \
BIT(PMU_ICG_FUNC_ENA_UART0) | \
BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \
) \
.backup_clk = 0xffffffff, \
}

const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode)
Expand Down
2 changes: 1 addition & 1 deletion components/esp_hw_support/port/esp32c61/private_include/pmu_param.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -90,7 +90,7 @@ const pmu_hp_system_analog_param_t* pmu_hp_system_analog_param_default(pmu_hp_mo

typedef struct {
pmu_hp_backup_reg_t retention;
uint32_t backup_clk;
uint32_t backup_clk; // icg_func
} pmu_hp_system_retention_param_t;

const pmu_hp_system_retention_param_t* pmu_hp_system_retention_param_default(pmu_hp_mode_t mode);
Expand Down
6 changes: 2 additions & 4 deletions components/esp_hw_support/port/esp32c61/rtc_clk.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -327,17 +327,15 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
void rtc_clk_cpu_freq_set_xtal(void)
{
rtc_clk_cpu_set_to_default_config();
// We don't turn off the bbpll if some consumers depend on bbpll
if (!s_bbpll_digi_consumers_ref_count) {
rtc_clk_bbpll_disable();
}
rtc_clk_bbpll_disable();
}

void rtc_clk_cpu_set_to_default_config(void)
{
int freq_mhz = (int)rtc_clk_xtal_freq_get();

rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep
}

void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
Expand Down
5 changes: 3 additions & 2 deletions components/esp_hw_support/port/esp32h2/include/soc/rtc.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -354,8 +354,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
* rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
* Assumes that XTAL frequency has been determined — don't call in startup code.
*
* @note On ESP32H2, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be
* turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL.
* @note This function always disables BBPLL after switching the CPU clock source to XTAL for power saving purpose.
* If this is unwanted, please use rtc_clk_cpu_freq_set_config. It helps to check whether USB Serial JTAG is in use,
* if so, then BBPLL will not be turned off.
*/
void rtc_clk_cpu_freq_set_xtal(void);

Expand Down
37 changes: 3 additions & 34 deletions components/esp_hw_support/port/esp32h2/pmu_param.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -290,18 +290,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
.hp_sleep2active_backup_en = 0, \
.hp_modem2active_backup_en = 0, \
}, \
.backup_clk = ( \
BIT(PMU_ICG_FUNC_ENA_GDMA) \
| BIT(PMU_ICG_FUNC_ENA_REGDMA) \
| BIT(PMU_ICG_FUNC_ENA_TG0) \
| BIT(PMU_ICG_FUNC_ENA_HPBUS) \
| BIT(PMU_ICG_FUNC_ENA_MSPI) \
| BIT(PMU_ICG_FUNC_ENA_IOMUX) \
| BIT(PMU_ICG_FUNC_ENA_SPI2) \
| BIT(PMU_ICG_FUNC_ENA_SEC) \
| BIT(PMU_ICG_FUNC_ENA_PWM) \
| BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \
| BIT(PMU_ICG_FUNC_ENA_UART0)), \
.backup_clk = 0xffffffff, \
}

#define PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT() { \
Expand All @@ -313,16 +302,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
.hp_sleep2modem_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 1), \
.hp_sleep2modem_backup_en = 0, \
}, \
.backup_clk = (BIT(PMU_ICG_FUNC_ENA_REGDMA) \
| BIT(PMU_ICG_FUNC_ENA_TG0) \
| BIT(PMU_ICG_FUNC_ENA_HPBUS) \
| BIT(PMU_ICG_FUNC_ENA_MSPI) \
| BIT(PMU_ICG_FUNC_ENA_IOMUX) \
| BIT(PMU_ICG_FUNC_ENA_SPI2) \
| BIT(PMU_ICG_FUNC_ENA_SEC) \
| BIT(PMU_ICG_FUNC_ENA_PWM) \
| BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \
| BIT(PMU_ICG_FUNC_ENA_UART0)), \
.backup_clk = 0xffffffff, \
}

#define PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() { \
Expand All @@ -339,18 +319,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
.hp_modem2sleep_backup_en = 0, \
.hp_active2sleep_backup_en = 0, \
}, \
.backup_clk = ( \
BIT(PMU_ICG_FUNC_ENA_GDMA) \
| BIT(PMU_ICG_FUNC_ENA_REGDMA) \
| BIT(PMU_ICG_FUNC_ENA_TG0) \
| BIT(PMU_ICG_FUNC_ENA_HPBUS) \
| BIT(PMU_ICG_FUNC_ENA_MSPI) \
| BIT(PMU_ICG_FUNC_ENA_IOMUX) \
| BIT(PMU_ICG_FUNC_ENA_SPI2) \
| BIT(PMU_ICG_FUNC_ENA_SEC) \
| BIT(PMU_ICG_FUNC_ENA_PWM) \
| BIT(PMU_ICG_FUNC_ENA_SYSTIMER) \
| BIT(PMU_ICG_FUNC_ENA_UART0)), \
.backup_clk = 0xffffffff, \
}

const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode)
Expand Down
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