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Merge branch 'chip/esp32c61_mp_support_wifi' into 'master'
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esp32c61 mp support wifi

See merge request espressif/esp-idf!32960
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xuxiao111 committed Sep 2, 2024
2 parents 7cf872e + 7c9109d commit a3274e5
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164 changes: 164 additions & 0 deletions components/esp_coex/esp32c61/esp_coex_adapter.c
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/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <stddef.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <assert.h>
#include <pthread.h>

#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/queue.h"
#include "freertos/semphr.h"
#include "freertos/portmacro.h"
#include "esp_heap_caps.h"
#include "esp_timer.h"
#include "soc/rtc.h"
#include "esp_private/esp_clk.h"
#include "private/esp_coexist_adapter.h"
#include "esp32c61/rom/ets_sys.h"

#define TAG "esp_coex_adapter"

#define OSI_FUNCS_TIME_BLOCKING 0xffffffff

bool IRAM_ATTR esp_coex_common_env_is_chip_wrapper(void)
{
#ifdef CONFIG_IDF_ENV_FPGA
return false;
#else
return true;
#endif
}

void *esp_coex_common_spin_lock_create_wrapper(void)
{
portMUX_TYPE tmp = portMUX_INITIALIZER_UNLOCKED;
void *mux = malloc(sizeof(portMUX_TYPE));

if (mux) {
memcpy(mux, &tmp, sizeof(portMUX_TYPE));
return mux;
}
return NULL;
}

uint32_t IRAM_ATTR esp_coex_common_int_disable_wrapper(void *wifi_int_mux)
{
if (xPortInIsrContext()) {
portENTER_CRITICAL_ISR(wifi_int_mux);
} else {
portENTER_CRITICAL(wifi_int_mux);
}

return 0;
}

void IRAM_ATTR esp_coex_common_int_restore_wrapper(void *wifi_int_mux, uint32_t tmp)
{
if (xPortInIsrContext()) {
portEXIT_CRITICAL_ISR(wifi_int_mux);
} else {
portEXIT_CRITICAL(wifi_int_mux);
}
}

void IRAM_ATTR esp_coex_common_task_yield_from_isr_wrapper(void)
{
portYIELD_FROM_ISR();
}

void *esp_coex_common_semphr_create_wrapper(uint32_t max, uint32_t init)
{
return (void *)xSemaphoreCreateCounting(max, init);
}

void esp_coex_common_semphr_delete_wrapper(void *semphr)
{
vSemaphoreDelete(semphr);
}

int32_t esp_coex_common_semphr_take_wrapper(void *semphr, uint32_t block_time_tick)
{
if (block_time_tick == OSI_FUNCS_TIME_BLOCKING) {
return (int32_t)xSemaphoreTake(semphr, portMAX_DELAY);
} else {
return (int32_t)xSemaphoreTake(semphr, block_time_tick);
}
}

int32_t esp_coex_common_semphr_give_wrapper(void *semphr)
{
return (int32_t)xSemaphoreGive(semphr);
}

void IRAM_ATTR esp_coex_common_timer_disarm_wrapper(void *timer)
{
ets_timer_disarm(timer);
}

void esp_coex_common_timer_done_wrapper(void *ptimer)
{
ets_timer_done(ptimer);
}

void esp_coex_common_timer_setfn_wrapper(void *ptimer, void *pfunction, void *parg)
{
ets_timer_setfn(ptimer, pfunction, parg);
}

void IRAM_ATTR esp_coex_common_timer_arm_us_wrapper(void *ptimer, uint32_t us, bool repeat)
{
ets_timer_arm_us(ptimer, us, repeat);
}

uint32_t esp_coex_common_clk_slowclk_cal_get_wrapper(void)
{
/* The bit width of WiFi light sleep clock calibration is 12 while the one of
* system is 19. It should shift 19 - 12 = 7.
*/
return (esp_clk_slowclk_cal_get() >> (RTC_CLK_CAL_FRACT - SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH));
}

void *IRAM_ATTR esp_coex_common_malloc_internal_wrapper(size_t size)
{
return heap_caps_malloc(size, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
}

/* static wrapper */

static int32_t IRAM_ATTR esp_coex_semphr_take_from_isr_wrapper(void *semphr, void *hptw)
{
return (int32_t)xSemaphoreTakeFromISR(semphr, hptw);
}

static int32_t IRAM_ATTR esp_coex_semphr_give_from_isr_wrapper(void *semphr, void *hptw)
{
return (int32_t)xSemaphoreGiveFromISR(semphr, hptw);
}

coex_adapter_funcs_t g_coex_adapter_funcs = {
._version = COEX_ADAPTER_VERSION,
._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper,
._semphr_create = esp_coex_common_semphr_create_wrapper,
._semphr_delete = esp_coex_common_semphr_delete_wrapper,
._semphr_take_from_isr = esp_coex_semphr_take_from_isr_wrapper,
._semphr_give_from_isr = esp_coex_semphr_give_from_isr_wrapper,
._semphr_take = esp_coex_common_semphr_take_wrapper,
._semphr_give = esp_coex_common_semphr_give_wrapper,
._is_in_isr = xPortInIsrContext,
._malloc_internal = esp_coex_common_malloc_internal_wrapper,
._free = free,
._esp_timer_get_time = esp_timer_get_time,
._env_is_chip = esp_coex_common_env_is_chip_wrapper,
._timer_disarm = esp_coex_common_timer_disarm_wrapper,
._timer_done = esp_coex_common_timer_done_wrapper,
._timer_setfn = esp_coex_common_timer_setfn_wrapper,
._timer_arm_us = esp_coex_common_timer_arm_us_wrapper,
._magic = COEX_ADAPTER_MAGIC,
};
2 changes: 1 addition & 1 deletion components/esp_coex/test_md5/test_md5.sh
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Expand Up @@ -22,7 +22,7 @@ case $IDF_TARGET in
esp32s3)
PREFIX=xtensa-esp32s3-elf-
;;
esp32c2|esp32c3|esp32c6|esp32h2|esp32c5)
esp32c2|esp32c3|esp32c6|esp32h2|esp32c5|esp32c61)
PREFIX=riscv32-esp-elf-
;;
*)
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4 changes: 2 additions & 2 deletions components/esp_phy/CMakeLists.txt
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Expand Up @@ -4,8 +4,8 @@ if(${idf_target} STREQUAL "linux")
return() # This component is not supported by the POSIX/Linux simulator
endif()

if(IDF_TARGET STREQUAL "esp32p4" OR IDF_TARGET STREQUAL "esp32c61")
# TODO: IDF-7460, IDF-8851, IDF-9553
if(IDF_TARGET STREQUAL "esp32p4")
# TODO: IDF-7460
idf_component_register()
return()
endif()
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24 changes: 24 additions & 0 deletions components/esp_phy/esp32c61/include/btbb_retention_reg.h
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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

#pragma once

#ifdef __cplusplus
extern "C" {
#endif

// btbb sleep retention reg

#define BB_PART_0_SIZE 93
#define BB_PART_1_SIZE 62
#define BB_PART_2_SIZE 19
#define BB_PART_0_ADDR 0x600A2000
#define BB_PART_1_ADDR 0x600A2800
#define BB_PART_2_ADDR 0x600A2C00

#ifdef __cplusplus
}
#endif
64 changes: 64 additions & 0 deletions components/esp_phy/esp32c61/include/phy_init_data.h
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/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/

#ifndef PHY_INIT_DATA_H
#define PHY_INIT_DATA_H /* don't use #pragma once here, we compile this file sometimes */
#include <stdint.h>
#include "esp_phy_init.h"
#include "sdkconfig.h"

#ifdef __cplusplus
extern "C" {
#endif
// constrain a value between 'low' and 'high', inclusive
#define LIMIT(val, low, high) ((val < low) ? low : (val > high) ? high : val)
#define PHY_INIT_MAGIC "PHYINIT"
#define PHY_INIT_MAGIC_LEN 8 // should be strlen(PHY_INIT_MAGIC) + 1

// define the lowest tx power as LOWEST_PHY_TX_POWER
#define PHY_TX_POWER_LOWEST LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 52)
#define PHY_TX_POWER_OFFSET 2
#define PHY_TX_POWER_NUM 14

#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
#define PHY_CRC_ALGORITHM 1
#define PHY_COUNTRY_CODE_LEN 2
#define PHY_INIT_DATA_TYPE_OFFSET 254
#define PHY_SUPPORT_MULTIPLE_BIN_OFFSET 253
#endif

extern const char phy_init_magic_pre[];
extern const esp_phy_init_data_t phy_init_data;
extern const char phy_init_magic_post[];

#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
/**
* @brief PHY init data control information structure
*/
typedef struct {
uint8_t control_info_checksum[4]; /*!< 4-byte control information checksum */
uint8_t multiple_bin_checksum[4]; /*!< 4-byte multiple bin checksum */
uint8_t check_algorithm; /*!< check algorithm */
uint8_t version; /*!< PHY init data bin version */
uint8_t number; /*!< PHY init data bin number */
uint8_t length[2]; /*!< Length of each PHY init data bin */
uint8_t reserved[19]; /*!< 19-byte reserved */
} __attribute__ ((packed)) phy_control_info_data_t;

/**
* @brief Country corresponds to PHY init data type structure
*/
typedef struct {
char cc[PHY_COUNTRY_CODE_LEN];
uint8_t type;
} phy_country_to_bin_type_t;
#endif

#ifdef __cplusplus
}
#endif

#endif /* PHY_INIT_DATA_H */
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