Merge branch 'feat/esp32c5_mp_uart_support' into 'master'

feat(uart): support HP/LP uart on ESP32C5 MP Closes IDF-8722 See merge request espressif/esp-idf!31024
espressif · Jun 12, 2024 · 3ec99db · 3ec99db
2 parents 3af0335 + ed6ca69
commit 3ec99db
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Showing 10 changed files with 93 additions and 41 deletions.
diff --git a/components/hal/esp32c5/include/hal/uart_ll.h b/components/hal/esp32c5/include/hal/uart_ll.h
@@ -112,7 +112,7 @@ FORCE_INLINE_ATTR void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *sou
     switch (LP_CLKRST.lpperi.lp_uart_clk_sel) {
     default:
     case 0:
-        *source_clk = (soc_module_clk_t)LP_UART_SCLK_LP_FAST;
+        *source_clk = (soc_module_clk_t)LP_UART_SCLK_RC_FAST;
         break;
     case 1:
         *source_clk = (soc_module_clk_t)LP_UART_SCLK_XTAL_D2;
@@ -130,7 +130,7 @@ static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_
 {
     (void)hw;
     switch (src_clk) {
-    case LP_UART_SCLK_LP_FAST:
+    case LP_UART_SCLK_RC_FAST:
         LP_CLKRST.lpperi.lp_uart_clk_sel = 0;
         break;
     case LP_UART_SCLK_XTAL_D2:
@@ -167,12 +167,7 @@ FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, ui
     // an integer part and a fractional part.
     hw->clkdiv_sync.clkdiv_int = clk_div >> 4;
     hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // TODO: [ESP32c5] IDF-8633 Not found sclk_div_num for LP_UART
-    abort();
-#endif
     uart_ll_update(hw);
 }
 
@@ -437,12 +432,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr
     div_reg.val = hw->clkdiv_sync.val;
     int sclk_div;
     if ((hw) == &LP_UART) {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
         sclk_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-        // TODO: [ESP32c5] IDF-8633 Not found sclk_div_num for LP_UART
-        abort();
-#endif
     } else {
         sclk_div = UART_LL_PCR_REG_U32_GET(hw, sclk_conf, sclk_div_num) + 1;
     }

diff --git a/components/soc/esp32c5/beta3/include/soc/clk_tree_defs.h b/components/soc/esp32c5/beta3/include/soc/clk_tree_defs.h
@@ -19,7 +19,7 @@ extern "C" {
  *
  * 2) External 40/48MHz Crystal Clock: XTAL
  *
- * 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referrred as SOSC in TRM or reg. description)
+ * 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referred as SOSC in TRM or reg. description)
  *
  *    This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
  *    can be computed in runtime through calibration.
@@ -250,15 +250,15 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of LP_UART
  */
-#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2}
+#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL_D2}
 
 /**
  * @brief Type of LP_UART clock source
  */
 typedef enum {
-    LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST,        /*!< LP_UART source clock is LP(RTC)_FAST */
+    LP_UART_SCLK_RC_FAST = SOC_MOD_CLK_RC_FAST,         /*!< LP_UART source clock is RC_FAST */
     LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2,         /*!< LP_UART source clock is XTAL_D2 */
-    LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST,        /*!< LP_UART source clock default choice is LP(RTC)_FAST */
+    LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL_D2,         /*!< LP_UART source clock default choice is RC_FAST */
 } soc_periph_lp_uart_clk_src_t;
 
 //////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////

diff --git a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
@@ -111,6 +111,10 @@ config SOC_SECURE_BOOT_SUPPORTED
     bool
     default y
 
+config SOC_LP_PERIPHERALS_SUPPORTED
+    bool
+    default y
+
 config SOC_SPI_FLASH_SUPPORTED
     bool
     default y
@@ -723,10 +727,26 @@ config SOC_LP_UART_FIFO_LEN
     int
     default 16
 
+config SOC_UART_BITRATE_MAX
+    int
+    default 5000000
+
 config SOC_UART_SUPPORT_XTAL_CLK
     bool
     default y
 
+config SOC_UART_SUPPORT_WAKEUP_INT
+    bool
+    default y
+
+config SOC_UART_HAS_LP_UART
+    bool
+    default y
+
+config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
+    bool
+    default y
+
 config SOC_PM_SUPPORT_MODEM_PD
     bool
     default y

diff --git a/components/soc/esp32c5/mp/include/soc/clk_tree_defs.h b/components/soc/esp32c5/mp/include/soc/clk_tree_defs.h
@@ -247,23 +247,39 @@ typedef enum {  // TODO: [ESP32C5] IDF-8727 (inherit from C6)
 
 ///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
 
+/**
+ * @brief Array initializer for all supported clock sources of UART
+ */
+#define SOC_UART_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
+
 /**
  * @brief Type of UART clock source, reserved for the legacy UART driver
  */
-typedef enum {  // TODO: [ESP32C5] IDF-8722 (inherit from C6)
+typedef enum {
     UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M,          /*!< UART source clock is PLL_F80M */
     UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST,                /*!< UART source clock is RC_FAST */
     UART_SCLK_XTAL = SOC_MOD_CLK_XTAL,                  /*!< UART source clock is XTAL */
+#if SOC_CLK_TREE_SUPPORTED
     UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M,           /*!< UART source clock default choice is PLL_F80M */
+#else
+    UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL,               /*!< UART source clock default choice is XTAL for FPGA environment*/
+#endif
 } soc_periph_uart_clk_src_legacy_t;
 
+/**
+ * @brief Array initializer for all supported clock sources of LP_UART
+ */
+#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL_D2}
+
 /**
  * @brief Type of LP_UART clock source
  */
-typedef enum {  // TODO: [ESP32C5] IDF-8633 (inherit from C6)
-    LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST,        /*!< LP_UART source clock is LP(RTC)_FAST */
+typedef enum {
+    LP_UART_SCLK_RC_FAST = SOC_MOD_CLK_RC_FAST,         /*!< LP_UART source clock is RC_FAST */
     LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2,         /*!< LP_UART source clock is XTAL_D2 */
-    LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST,        /*!< LP_UART source clock default choice is LP(RTC)_FAST */
+
+    //TODO: IDF-10034
+    LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL_D2,         /*!< LP_UART source clock default choice is XTAL_D2 */
 } soc_periph_lp_uart_clk_src_t;
 
 //////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////

diff --git a/components/soc/esp32c5/mp/include/soc/lp_uart_struct.h b/components/soc/esp32c5/mp/include/soc/lp_uart_struct.h
@@ -844,7 +844,22 @@ typedef union {
  */
 typedef union {
     struct {
-        uint32_t reserved_0:24;
+        /** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
+         *  The  denominator of the frequency divider factor.
+         *  Only available to LP UART instance
+         */
+        uint32_t sclk_div_b:6;
+        /** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
+         *  The numerator of the frequency divider factor.
+         *  Only available to LP UART instance
+         */
+        uint32_t sclk_div_a:6;
+        /** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
+         *  The integral part of the frequency divider factor.
+         *  Only available to LP UART instance
+         */
+        uint32_t sclk_div_num:8;
+        uint32_t reserved_20:4;
         /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
          *  Configures whether or not to enable LP UART TX clock.\\
          *  0: Disable\\

diff --git a/components/soc/esp32c5/mp/include/soc/soc_caps.h b/components/soc/esp32c5/mp/include/soc/soc_caps.h
@@ -19,7 +19,7 @@
 /*-------------------------- COMMON CAPS ---------------------------------------*/
 // #define SOC_ADC_SUPPORTED               1  // TODO: [ESP32C5] IDF-8701
 // #define SOC_DEDICATED_GPIO_SUPPORTED    1  // TODO: [ESP32C5] IDF-8725
-#define SOC_UART_SUPPORTED              1     // TODO: [ESP32C5] IDF-8722
+#define SOC_UART_SUPPORTED              1
 #define SOC_GDMA_SUPPORTED              1
 #define SOC_AHB_GDMA_SUPPORTED          1
 #define SOC_GPTIMER_SUPPORTED           1
@@ -61,7 +61,7 @@
 // #define SOC_PAU_SUPPORTED               1  // TODO: [ESP32C5] IDF-8638
 // #define SOC_LP_TIMER_SUPPORTED          1  // TODO: [ESP32C5] IDF-8636
 // #define SOC_LP_AON_SUPPORTED            1  // TODO: [ESP32C5] IDF-8638
-// #define SOC_LP_PERIPHERALS_SUPPORTED    1  // TODO: [ESP32C5] IDF-8695, IDF-8723, IDF-8719
+#define SOC_LP_PERIPHERALS_SUPPORTED    1
 // #define SOC_LP_I2C_SUPPORTED            1  // TODO: [ESP32C5] IDF-8634
 // #define SOC_ULP_LP_UART_SUPPORTED       1  // TODO: [ESP32C5] IDF-8633
 // #define SOC_CLK_TREE_SUPPORTED          1  // TODO: [ESP32C5] IDF-8642
@@ -490,14 +490,15 @@
 #define SOC_UART_LP_NUM                 (1U)
 #define SOC_UART_FIFO_LEN               (128)       /*!< The UART hardware FIFO length */
 #define SOC_LP_UART_FIFO_LEN            (16)        /*!< The LP UART hardware FIFO length */
-// #define SOC_UART_BITRATE_MAX            (5000000)   /*!< Max bit rate supported by UART */
+#define SOC_UART_BITRATE_MAX            (5000000)   /*!< Max bit rate supported by UART */
 // #define SOC_UART_SUPPORT_PLL_F80M_CLK   (1)         /*!< Support PLL_F80M as the clock source */
-// #define SOC_UART_SUPPORT_RTC_CLK        (1)         /*!< Support RTC clock as the clock source */
+// #define SOC_UART_SUPPORT_RTC_CLK        (1)         /*!< Support RTC clock as the clock source */ // TODO: [ESP32C5] IDF-8642
 #define SOC_UART_SUPPORT_XTAL_CLK       (1)         /*!< Support XTAL clock as the clock source */
-// #define SOC_UART_SUPPORT_WAKEUP_INT     (1)         /*!< Support UART wakeup interrupt */
+#define SOC_UART_SUPPORT_WAKEUP_INT     (1)         /*!< Support UART wakeup interrupt */
+#define SOC_UART_HAS_LP_UART            (1)         /*!< Support LP UART */
 
 // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
-// #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
+#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
 
 /*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
 // #define SOC_COEX_HW_PTI                 (1)

diff --git a/components/soc/esp32c5/mp/include/soc/uart_channel.h b/components/soc/esp32c5/mp/include/soc/uart_channel.h
@@ -8,13 +8,11 @@
 
 #pragma once
 
-// TODO: [ESP32C5] IDF-8722
-
 //UART channels
-#define UART_GPIO16_DIRECT_CHANNEL      UART_NUM_0
-#define UART_NUM_0_TXD_DIRECT_GPIO_NUM  16
-#define UART_GPIO17_DIRECT_CHANNEL      UART_NUM_0
-#define UART_NUM_0_RXD_DIRECT_GPIO_NUM  17
+#define UART_GPIO11_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_TXD_DIRECT_GPIO_NUM  11
+#define UART_GPIO12_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_RXD_DIRECT_GPIO_NUM  12
 
-#define UART_TXD_GPIO16_DIRECT_CHANNEL  UART_GPIO16_DIRECT_CHANNEL
-#define UART_RXD_GPIO17_DIRECT_CHANNEL  UART_GPIO17_DIRECT_CHANNEL
+#define UART_TXD_GPIO11_DIRECT_CHANNEL  UART_GPIO11_DIRECT_CHANNEL
+#define UART_RXD_GPIO12_DIRECT_CHANNEL  UART_GPIO12_DIRECT_CHANNEL
diff --git a/components/soc/esp32c5/mp/include/soc/uart_pins.h b/components/soc/esp32c5/mp/include/soc/uart_pins.h
@@ -8,8 +8,6 @@
 
 #include "soc/io_mux_reg.h"
 
-// TODO: [ESP32C5] IDF-8722
-
 /* Specify the number of pins for UART */
 #define SOC_UART_PINS_COUNT  (4)
 

diff --git a/components/soc/esp32c5/mp/include/soc/uart_struct.h b/components/soc/esp32c5/mp/include/soc/uart_struct.h
@@ -20,8 +20,7 @@ typedef union {
          *  Represents the data UART $n read from FIFO.\\
          *  Measurement unit: byte.
          */
-        uint32_t rxfifo_rd_byte:8;
-        uint32_t reserved_8:24;
+        uint32_t rxfifo_rd_byte:32;
     };
     uint32_t val;
 } uart_fifo_reg_t;
@@ -947,7 +946,22 @@ typedef union {
  */
 typedef union {
     struct {
-        uint32_t reserved_0:24;
+        /** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
+         *  The  denominator of the frequency divider factor.'
+         *  Only available to LP UART instance
+         */
+        uint32_t sclk_div_b:6;
+        /** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
+         *  The numerator of the frequency divider factor.
+         *  Only available to LP UART instance
+         */
+        uint32_t sclk_div_a:6;
+        /** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
+         *  The integral part of the frequency divider factor.
+         *  Only available to LP UART instance
+         */
+        uint32_t sclk_div_num:8;
+        uint32_t reserved_20:4;
         /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
          *  Configures whether or not to enable UART TX clock.\\
          *  0: Disable\\

diff --git a/examples/protocols/.build-test-rules.yml b/examples/protocols/.build-test-rules.yml
@@ -174,7 +174,7 @@ examples/protocols/modbus:
   disable:
     - if: IDF_TARGET == "esp32c5"
       temporary: true
-      reason: not supported yet  # TODO: [ESP32C5] IDF-8722, IDF-8697
+      reason: not supported yet  # TODO: [ESP32C5] IDF-8697
   depends_filepatterns:
     - examples/protocols/modbus/mb_example_common/**/*