Merge branch 'feature/esp32c5_mp_gpio_support' into 'master'

C5 gpio support and update docs

See merge request espressif/esp-idf!30792

components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.heap.ld

@@ -76,5 +76,6 @@ PROVIDE (multi_heap_aligned_alloc = multi_heap_aligned_alloc_impl);
 PROVIDE (multi_heap_aligned_free = multi_heap_aligned_free_impl);
 PROVIDE (multi_heap_check = multi_heap_check);
 PROVIDE (multi_heap_set_lock = multi_heap_set_lock);
+PROVIDE (multi_heap_os_funcs_init = multi_heap_mutex_init);
 PROVIDE (multi_heap_internal_lock = multi_heap_internal_lock);
 PROVIDE (multi_heap_internal_unlock = multi_heap_internal_unlock);

components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.pp.ld

@@ -62,7 +62,7 @@ ic_get_he_rts_threshold_bytes = 0x40000c88;
 lmacAdjustTimestamp = 0x40000c8c;
 lmacDiscardAgedMSDU = 0x40000c90;
 lmacDiscardMSDU = 0x40000c94;
-/*lmacEndFrameExchangeSequence = 0x40000c98;*/
+lmacEndFrameExchangeSequence = 0x40000c98;
 lmacIsIdle = 0x40000c9c;
 lmacIsLongFrame = 0x40000ca0;
 lmacMSDUAged = 0x40000ca4;

components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.rvfp.ld

@@ -18,45 +18,108 @@
  ***************************************/
 
 /* Functions */
-_rvfp__addsf3 = 0x40000a2c;
-_rvfp__eqsf2 = 0x40000a30;
-_rvfp__extendsfdf2 = 0x40000a34;
-_rvfp__fixsfsi = 0x40000a38;
-_rvfp__fixunssfsi = 0x40000a3c;
-_rvfp__floatdisf = 0x40000a40;
-_rvfp__floatsisf = 0x40000a44;
-_rvfp__floatundisf = 0x40000a48;
-_rvfp__floatunsisf = 0x40000a4c;
-_rvfp__gesf2 = 0x40000a50;
-_rvfp__gtsf2 = 0x40000a54;
-_rvfp__lesf2 = 0x40000a58;
-_rvfp__ltsf2 = 0x40000a5c;
-_rvfp__mulsf3 = 0x40000a60;
-_rvfp__nesf2 = 0x40000a64;
-_rvfp__subsf3 = 0x40000a68;
-_rvfp__truncdfsf2 = 0x40000a6c;
+__addsf3 = 0x40000a2c;
+__eqsf2 = 0x40000a30;
+__extendsfdf2 = 0x40000a34;
+__fixsfsi = 0x40000a38;
+__fixunssfsi = 0x40000a3c;
+__floatdisf = 0x40000a40;
+__floatsisf = 0x40000a44;
+__floatundisf = 0x40000a48;
+__floatunsisf = 0x40000a4c;
+__gesf2 = 0x40000a50;
+__gtsf2 = 0x40000a54;
+__lesf2 = 0x40000a58;
+__ltsf2 = 0x40000a5c;
+__mulsf3 = 0x40000a60;
+__nesf2 = 0x40000a64;
+__subsf3 = 0x40000a68;
+__truncdfsf2 = 0x40000a6c;
 
 
 /***************************************
  Group rvfplibdf
  ***************************************/
 
 /* Functions */
-_rvfp__adddf3 = 0x40000a70;
-_rvfp__eqdf2 = 0x40000a74;
-_rvfp__fixdfdi = 0x40000a78;
-_rvfp__fixdfsi = 0x40000a7c;
-_rvfp__fixsfdi = 0x40000a80;
-_rvfp__fixunsdfsi = 0x40000a84;
-_rvfp__fixunssfdi = 0x40000a88;
-_rvfp__floatdidf = 0x40000a8c;
-_rvfp__floatsidf = 0x40000a90;
-_rvfp__floatundidf = 0x40000a94;
-_rvfp__floatunsidf = 0x40000a98;
-_rvfp__gedf2 = 0x40000a9c;
-_rvfp__gtdf2 = 0x40000aa0;
-_rvfp__ledf2 = 0x40000aa4;
-_rvfp__ltdf2 = 0x40000aa8;
-_rvfp__muldf3 = 0x40000aac;
-_rvfp__nedf2 = 0x40000ab0;
-_rvfp__subdf3 = 0x40000ab4;
+__adddf3 = 0x40000a70;
+__eqdf2 = 0x40000a74;
+__fixdfdi = 0x40000a78;
+__fixdfsi = 0x40000a7c;
+__fixsfdi = 0x40000a80;
+__fixunsdfsi = 0x40000a84;
+__fixunssfdi = 0x40000a88;
+__floatdidf = 0x40000a8c;
+__floatsidf = 0x40000a90;
+__floatundidf = 0x40000a94;
+__floatunsidf = 0x40000a98;
+__gedf2 = 0x40000a9c;
+__gtdf2 = 0x40000aa0;
+__ledf2 = 0x40000aa4;
+__ltdf2 = 0x40000aa8;
+__muldf3 = 0x40000aac;
+__nedf2 = 0x40000ab0;
+__subdf3 = 0x40000ab4;
+
+/***************************************
+ Group libgcc
+***************************************/
+
+/* Functions */
+__divsf3 = 0x400008c0;
+__negsf2 = 0x400008e8;
+__powisf2 = 0x400008f0;
+__unordsf2 = 0x400008fc;
+__absvdi2 = 0x40000900;
+__absvsi2 = 0x40000904;
+__addvdi3 = 0x4000090c;
+__addvsi3 = 0x40000910;
+__ashldi3 = 0x40000914;
+__ashrdi3 = 0x40000918;
+__bswapdi2 = 0x4000091c;
+__bswapsi2 = 0x40000920;
+__clear_cache = 0x40000924;
+__clrsbdi2 = 0x40000928;
+__clrsbsi2 = 0x4000092c;
+__clzdi2 = 0x40000930;
+__clzsi2 = 0x40000934;
+__cmpdi2 = 0x40000938;
+__ctzdi2 = 0x4000093c;
+__ctzsi2 = 0x40000940;
+__divdc3 = 0x40000944;
+__divdf3 = 0x40000948;
+__divdi3 = 0x4000094c;
+__divsc3 = 0x40000950;
+__divsi3 = 0x40000954;
+__ffsdi2 = 0x40000960;
+__ffssi2 = 0x40000964;
+__gcc_bcmp = 0x40000998;
+__lshrdi3 = 0x400009a8;
+__moddi3 = 0x400009b0;
+__modsi3 = 0x400009b4;
+__muldc3 = 0x400009b8;
+__muldi3 = 0x400009c0;
+__mulsc3 = 0x400009c4;
+__mulsi3 = 0x400009c8;
+__mulvdi3 = 0x400009cc;
+__mulvsi3 = 0x400009d0;
+__negdf2 = 0x400009d8;
+__negdi2 = 0x400009dc;
+__negvdi2 = 0x400009e0;
+__negvsi2 = 0x400009e4;
+__paritysi2 = 0x400009e8;
+__popcountdi2 = 0x400009ec;
+__popcountsi2 = 0x400009f0;
+__powidf2 = 0x400009f4;
+__subvdi3 = 0x400009fc;
+__subvsi3 = 0x40000a00;
+__ucmpdi2 = 0x40000a04;
+__udivdi3 = 0x40000a08;
+__udivmoddi4 = 0x40000a0c;
+__udivsi3 = 0x40000a10;
+__udiv_w_sdiv = 0x40000a14;
+__umoddi3 = 0x40000a18;
+__umodsi3 = 0x40000a1c;
+__unorddf2 = 0x40000a20;
+__extenddftf2 = 0x40000a24;
+__trunctfdf2 = 0x40000a28;

components/espcoredump/src/core_dump_uart.c

@@ -154,7 +154,7 @@ static esp_err_t esp_core_dump_uart_hw_init(void)
 
     //Make sure txd/rxd are enabled
     // use direct reg access instead of gpio_pullup_dis which can cause exception when flash cache is disabled
-    REG_CLR_BIT(GPIO_PIN_REG_1, FUN_PU);
+    REG_CLR_BIT(GPIO_PIN_REG_1, FUN_PU); //TODO: IDF-9948
     gpio_hal_func_sel(&gpio_hal, U0RXD_GPIO_NUM, U0RXD_MUX_FUNC);
     gpio_hal_func_sel(&gpio_hal, U0TXD_GPIO_NUM, U0TXD_MUX_FUNC);
     ESP_COREDUMP_LOGI("Press Enter to print core dump to UART...");