boards: add USB HS 2.0 support for the Nucleo u5a5jz-q board (Issue z…

…ephyrproject-rtos#79823)

This board has the required clock crystal (X4) and jumper settings
present to enable the USB 2.0 HS support.

* Enable the HSE clock (16MHz)
* Flip the PLL1 configuration over to use the HSE clock, but still
  outputting 160MHz to sysclk/apbclk.
* Add the USB HS device tree node.
* Update the board documentation.

Signed-off-by: Adrian Chadd <adrian.chadd@meta.com>

boards/st/nucleo_u5a5zj_q/doc/index.rst

@@ -204,6 +204,8 @@ The Zephyr nucleo_u5a5zj_q board configuration supports the following hardware f
 +-----------+------------+-------------------------------------+
 | RTC       | on-chip    | rtc                                 |
 +-----------+------------+-------------------------------------+
+| USB       | on-chip    | USB 2.0 HS                          |
++-----------+------------+-------------------------------------+
 
 
 Other hardware features are not yet supported on this Zephyr port.
@@ -245,27 +247,34 @@ Default Zephyr Peripheral Mapping:
 - UART_2_TX : PD5
 - UART_2_RX : PD6
 - USER_PB : PC13
+- USB_DM : PA11
+- USB_DP : PA12
 
 System Clock
 ------------
 
 Nucleo U5A5ZJ Q System Clock could be driven by internal or external oscillator,
 as well as main PLL clock. By default System clock is driven by PLL clock at
-160MHz, driven by 4MHz medium speed internal oscillator.
+160MHz, driven by the 16MHz high speed oscillator.
 
 Serial Port
 -----------
 
 Nucleo U5A5ZJ Q board has 6 U(S)ARTs. The Zephyr console output is assigned to
 USART1. Default settings are 115200 8N1.
 
-
 Backup SRAM
 -----------
 
 In order to test backup SRAM you may want to disconnect VBAT from VDD. You can
 do it by removing ``SB50`` jumper on the back side of the board.
 
+Using USB
+---------
+
+USB 2.0 high speed (HS) operation requires the HSE clock source to be populated
+and enabled.  The Nucleo U5A5ZJ-Q includes the 16MHz oscillator and required
+jumper settings.
 
 Programming and Debugging
 *************************

boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi

@@ -55,22 +55,23 @@
 	status = "okay";
 };
 
-&clk_lse {
+/* This board has a 16MHz crystal attached */
+&clk_hse {
+	clock-frequency = <DT_FREQ_M(16)>;
 	status = "okay";
 };
 
-&clk_msis {
+&clk_lse {
 	status = "okay";
-	msi-range = <4>;
-	msi-pll-mode;
 };
 
 &pll1 {
-	div-m = <1>;
-	mul-n = <80>;
-	div-q = <2>;
-	div-r = <2>;
-	clocks = <&clk_msis>;
+	/* HSE 16MHz source, outputting 160MHz to sysclk and apbclk */
+	div-m = <4>; /* input divisor */
+	mul-n = <80>; /* VCO multiplication factor */
+	div-q = <2>; /* system clock divisor */
+	div-r = <2>; /* peripheral clock divisor */
+	clocks = <&clk_hse>;
 	status = "okay";
 };
 

boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts

@@ -74,3 +74,9 @@
 &gpdma1 {
 	status = "okay";
 };
+
+zephyr_udc0: &usbotg_hs {
+	pinctrl-0 = <&usb_otg_hs_dm_pa11 &usb_otg_hs_dp_pa12>;
+	pinctrl-names = "default";
+	status = "okay";
+};

boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml

@@ -21,5 +21,6 @@ supported:
   - backup_sram
   - dma
   - rtc
+  - usb_device
 ram: 2450
 flash: 4096