tlp/packetizer: Revert buffers in LitePCIeTLPHeaderInserter3DWs4DWs s…

…ince seems to introduce a regression.
enjoy-digital · Feb 26, 2024 · bb089a6 · bb089a6
1 parent 636c3e4
commit bb089a6
Showing 1 changed file with 0 additions and 2 deletions.
diff --git a/litepcie/tlp/packetizer.py b/litepcie/tlp/packetizer.py
@@ -21,9 +21,7 @@ def __init__(self, data_width, header_inserter_3dws_cls, header_inserter_4dws_cl
 
         # Header Inserters Modules.
         header_inserter_3dws = header_inserter_3dws_cls()
-        stream.BufferizeEndpoints({"sink"  : stream.DIR_SINK  })(header_inserter_3dws) # For Timings.
         header_inserter_4dws = header_inserter_4dws_cls()
-        stream.BufferizeEndpoints({"sink"  : stream.DIR_SINK  })(header_inserter_4dws) # For Timings.
         self.submodules += header_inserter_3dws, header_inserter_4dws
 
         # Header Inserters Sel.