bench/serwb: Cleanup/Uniformize targets.

enjoy-digital · Nov 17, 2023 · 0a1efa8 · 0a1efa8
1 parent f63e506
commit 0a1efa8
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Showing 6 changed files with 18 additions and 19 deletions.
diff --git a/bench/serwb/efinix_titanium_ti60_f225_dev_kit.py b/bench/serwb/efinix_titanium_ti60_f225_dev_kit.py
@@ -55,7 +55,6 @@
 
 class _CRG(LiteXModule):
     def __init__(self, platform, sys_clk_freq):
-        self.rst      = Signal()
         self.cd_sys   = ClockDomain()
         self.cd_sys4x = ClockDomain()
 
@@ -64,9 +63,10 @@ def __init__(self, platform, sys_clk_freq):
         clk25 = platform.request("clk25")
         rst_n = platform.request("user_btn", 0)
 
+
         # PLL
         self.pll = pll = TITANIUMPLL(platform)
-        self.comb += pll.reset.eq(~rst_n | self.rst)
+        self.comb += pll.reset.eq(~rst_n)
         pll.register_clkin(clk25, 25e6)
         # You can use CLKOUT0 only for clocks with a maximum frequency of 4x
         # (integer) of the reference clock. If all your system clocks do not fall within
@@ -75,7 +75,7 @@ def __init__(self, platform, sys_clk_freq):
         pll.create_clkout(self.cd_sys,     sys_clk_freq, with_reset=True, name="sys")
         pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq, with_reset=True, phase=90, name="sys4x")
 
-# BaseSoC ------------------------------------------------------------------------------------------
+# SerWBTestSoC ------------------------------------------------------------------------------------
 
 class SerWBTestSoC(SoCMini):
     mem_map = {
@@ -89,7 +89,7 @@ def __init__(self, platform, with_analyzer=True):
         # CRG --------------------------------------------------------------------------------------
         self.crg = _CRG(platform, sys_clk_freq)
 
-        # SoCCore ----------------------------------------------------------------------------------
+        # SoCMini ----------------------------------------------------------------------------------
         SoCMini.__init__(self, platform, sys_clk_freq,
             csr_data_with = 32,
             ident         = "LiteICLink SerWB bench on Efinix Titanium Ti60 F225 Dev Kit",

diff --git a/bench/serwb/efinix_trion_t120_bga576_dev_kit.py b/bench/serwb/efinix_trion_t120_bga576_dev_kit.py
@@ -72,7 +72,7 @@ def __init__(self, platform, sys_clk_freq):
         pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True, name="sys")
         pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq, phase=90, with_reset=True, name="sys4x")
 
-# BaseSoC ------------------------------------------------------------------------------------------
+# SerWBTestSoC ------------------------------------------------------------------------------------
 
 class SerWBTestSoC(SoCMini):
     mem_map = {
@@ -89,7 +89,7 @@ def __init__(self, platform, with_analyzer=True):
         # CRG --------------------------------------------------------------------------------------
         self.crg = _CRG(platform, sys_clk_freq)
 
-        # SoCCore ----------------------------------------------------------------------------------
+        # SoCMini ----------------------------------------------------------------------------------
         SoCMini.__init__(self, platform, sys_clk_freq,
             csr_data_with = 32,
             ident         = "LiteICLink SerWB bench on Efinix Trion T120 BGA576 Dev Kit",

diff --git a/bench/serwb/icebreaker.py b/bench/serwb/icebreaker.py
@@ -56,6 +56,9 @@ class SerWBTestSoC(SoCMini):
     def __init__(self, platform, loopback=False, with_analyzer=False):
         sys_clk_freq = int(24e6)
 
+        # CRG --------------------------------------------------------------------------------------
+        self.crg = _CRG(platform, sys_clk_freq)
+
         # SoCMini ----------------------------------------------------------------------------------
         SoCMini.__init__(self, platform, sys_clk_freq,
             csr_data_width = 32,
@@ -64,9 +67,6 @@ def __init__(self, platform, loopback=False, with_analyzer=False):
             with_uart      = True,
             uart_name      = "uartbone")
 
-        # CRG --------------------------------------------------------------------------------------
-        self.crg = _CRG(platform, sys_clk_freq)
-
         # SerWB ------------------------------------------------------------------------------------
         # SerWB simple test with a SerWB Master added as a Slave peripheral to the SoC and connected
         # to a SerWB Slave with a SRAM attached. Access to this SRAM is then tested from the main

diff --git a/bench/serwb/nexys_video.py b/bench/serwb/nexys_video.py
@@ -83,6 +83,9 @@ class SerWBTestSoC(SoCMini):
     def __init__(self, platform, low_speed=True, with_analyzer=True):
         sys_clk_freq = int(125e6)
 
+        # CRG --------------------------------------------------------------------------------------
+        self.crg = _CRG(platform, sys_clk_freq)
+
         # SoCMini ----------------------------------------------------------------------------------
         SoCMini.__init__(self, platform, sys_clk_freq,
             csr_data_width = 32,
@@ -91,10 +94,6 @@ def __init__(self, platform, low_speed=True, with_analyzer=True):
             with_uart      = True,
             uart_name      = "uartbone")
 
-        # CRG --------------------------------------------------------------------------------------
-        self.crg = _CRG(platform, sys_clk_freq)
-
-
         # SerWB ------------------------------------------------------------------------------------
         # SerWB simple test with a SerWB Master added as a Slave peripheral to the SoC and connected
         # to a SerWB Slave with a SRAM attached. Access to this SRAM is then tested from the main

diff --git a/bench/serwb/trellisboard.py b/bench/serwb/trellisboard.py
@@ -57,6 +57,9 @@ class SerWBTestSoC(SoCMini):
     def __init__(self, platform, loopback=False, with_analyzer=False):
         sys_clk_freq = int(50e6)
 
+        # CRG --------------------------------------------------------------------------------------
+        self.crg = _CRG(platform, sys_clk_freq)
+
         # SoCMini ----------------------------------------------------------------------------------
         SoCMini.__init__(self, platform, sys_clk_freq,
             csr_data_width = 32,
@@ -65,9 +68,6 @@ def __init__(self, platform, loopback=False, with_analyzer=False):
             with_uart      = True,
             uart_name      = "uartbone")
 
-        # CRG --------------------------------------------------------------------------------------
-        self.crg = _CRG(platform, sys_clk_freq)
-
         # SerWB ------------------------------------------------------------------------------------
         # SerWB simple test with a SerWB Master added as a Slave peripheral to the SoC and connected
         # to a SerWB Slave with a SRAM attached. Access to this SRAM is then tested from the main

diff --git a/bench/serwb/ulx3s.py b/bench/serwb/ulx3s.py
@@ -56,6 +56,9 @@ class SerWBTestSoC(SoCMini):
     def __init__(self, platform, loopback=False, with_analyzer=False):
         sys_clk_freq = int(50e6)
 
+        # CRG --------------------------------------------------------------------------------------
+        self.crg = _CRG(platform, sys_clk_freq)
+
         # SoCMini ----------------------------------------------------------------------------------
         SoCMini.__init__(self, platform, sys_clk_freq,
             csr_data_width = 32,
@@ -64,9 +67,6 @@ def __init__(self, platform, loopback=False, with_analyzer=False):
             with_uart      = True,
             uart_name      = "uartbone")
 
-        # CRG --------------------------------------------------------------------------------------
-        self.crg = _CRG(platform, sys_clk_freq)
-
         # SerWB ------------------------------------------------------------------------------------
         # SerWB simple test with a SerWB Master added as a Slave peripheral to the SoC and connected
         # to a SerWB Slave with a SRAM attached. Access to this SRAM is then tested from the main