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use new base test format
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@M0stafaRady
M0stafaRady committed Apr 15, 2024
1 parent a41b0c4 commit 7d0c8f2
Showing 1 changed file with 106 additions and 71 deletions.
177 changes: 106 additions & 71 deletions verify/uvm-python/test_lib.py
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,12 @@
from uvm.base.uvm_object_globals import UVM_LOW
from uvm.base.uvm_globals import run_test
from gpio8_interface.gpio8_if import gpio8_if
from EF_UVM.bus_env.bus_interface.bus_if import bus_apb_if, bus_irq_if, bus_ahb_if, bus_wb_if
from EF_UVM.bus_env.bus_interface.bus_if import (
bus_apb_if,
bus_irq_if,
bus_ahb_if,
bus_wb_if,
)
from cocotb_coverage.coverage import coverage_db
from cocotb.triggers import Event, First, Timer
from EF_UVM.bus_env.bus_regs import bus_regs
Expand Down Expand Up @@ -41,7 +46,7 @@
async def module_top(dut):
# profiler = cProfile.Profile()
# profiler.enable()
BUS_TYPE = cocotb.plusargs['BUS_TYPE']
BUS_TYPE = cocotb.plusargs["BUS_TYPE"]
pif = gpio8_if(dut)
if BUS_TYPE == "APB":
w_if = bus_apb_if(dut)
Expand Down Expand Up @@ -74,8 +79,8 @@ async def module_top(dut):

class gpio8_base_test(base_test):
def __init__(self, name="gpio8_first_test", parent=None):
BUS_TYPE = cocotb.plusargs['BUS_TYPE']
super().__init__(name, bus_type=BUS_TYPE , parent=parent)
BUS_TYPE = cocotb.plusargs["BUS_TYPE"]
super().__init__(name, bus_type=BUS_TYPE, parent=parent)
self.tag = name

def build_phase(self, phase):
Expand All @@ -84,7 +89,9 @@ def build_phase(self, phase):
self.set_type_override_by_type(ip_driver.get_type(), gpio8_driver.get_type())
self.set_type_override_by_type(ip_monitor.get_type(), gpio8_monitor.get_type())
self.set_type_override_by_type(ref_model.get_type(), gpio8_ref_model.get_type())
self.set_type_override_by_type(ip_coverage.get_type(), gpio8_coverage.get_type())
self.set_type_override_by_type(
ip_coverage.get_type(), gpio8_coverage.get_type()
)
self.set_type_override_by_type(ip_logger.get_type(), gpio8_logger.get_type())


Expand All @@ -96,7 +103,7 @@ def __init__(self, name="gpio8_all_out_test", parent=None):
super().__init__(name, parent)
self.tag = name

async def run_phase(self, phase):
async def main_phase(self, phase):
uvm_info(self.tag, f"Starting test {self.__class__.__name__}", UVM_LOW)
phase.raise_objection(self, f"{self.__class__.__name__} OBJECTED")
bus_gpio8_write_dir_seq = gpio8_write_dir_seq("gpio8_write_dir_seq")
Expand All @@ -108,14 +115,16 @@ async def run_phase(self, phase):
await bus_gpio8_write_datao_seq.start(self.bus_sqr)
phase.drop_objection(self, f"{self.__class__.__name__} drop objection")


uvm_component_utils(gpio8_all_out_test)


class gpio8_all_in_test(gpio8_base_test):
def __init__(self, name="gpio8_all_in_test", parent=None):
super().__init__(name, parent)
self.tag = name

async def run_phase(self, phase):
async def main_phase(self, phase):
uvm_info(self.tag, f"Starting test {self.__class__.__name__}", UVM_LOW)
phase.raise_objection(self, f"{self.__class__.__name__} OBJECTED")
bus_gpio8_write_dir_seq = gpio8_write_dir_seq("gpio8_write_dir_seq")
Expand All @@ -129,6 +138,7 @@ async def run_phase(self, phase):
await bus_gpio8_read_datai_seq.start(self.bus_sqr)
phase.drop_objection(self, f"{self.__class__.__name__} drop objection")


uvm_component_utils(gpio8_all_in_test)


Expand All @@ -137,7 +147,7 @@ def __init__(self, name="gpio8_rand_test", parent=None):
super().__init__(name, parent)
self.tag = name

async def run_phase(self, phase):
async def main_phase(self, phase):
uvm_info(self.tag, f"Starting test {self.__class__.__name__}", UVM_LOW)
phase.raise_objection(self, f"{self.__class__.__name__} OBJECTED")
bus_gpio8_write_dir_seq = gpio8_write_dir_seq("gpio8_write_dir_seq")
Expand All @@ -146,100 +156,125 @@ async def run_phase(self, phase):
bus_gpio8_read_datai_seq = gpio8_read_datai_seq("gpio8_read_datai_seq")
bus_gpio8_read_ris_seq = gpio8_read_ris_seq("gpio8_read_ris_seq")
bus_gpio8_write_ic_seq = gpio8_write_ic_seq("gpio8_write_ic_seq")
bus_gpio8_write_ic_seq.set_ic (0xFFFFFFFF)
bus_gpio8_write_ic_seq.set_ic(0xFFFFFFFF)

for _ in range(70):
rand_dir = random.choice (range(0, 0xFF))
rand_dir = random.choice(range(0, 0xFF))
bus_gpio8_write_dir_seq.set_gpios_dir(rand_dir)
bus_gpio8_write_datao_seq.set_gpios_dir(rand_dir)
ip_gpio_set_io_in_seq.set_gpios_dir(rand_dir)
await bus_gpio8_write_dir_seq.start(self.bus_sqr)
await bus_gpio8_write_datao_seq.start(self.bus_sqr)
await ip_gpio_set_io_in_seq.start(self.ip_sqr)
await bus_gpio8_read_ris_seq.start(self.bus_sqr) # read ris to check that it has the correct value
await bus_gpio8_write_ic_seq.start(self.bus_sqr) # clear all interrupts
await bus_gpio8_read_ris_seq.start(
self.bus_sqr
) # read ris to check that it has the correct value
await bus_gpio8_write_ic_seq.start(self.bus_sqr) # clear all interrupts
await bus_gpio8_read_datai_seq.start(self.bus_sqr)
phase.drop_objection(self, f"{self.__class__.__name__} drop objection")


uvm_component_utils(gpio8_rand_test)


class gpio8_interrupts_test(gpio8_base_test):
def __init__(self, name="gpio8_interrupts_test", parent=None):
super().__init__(name, parent)
self.tag = name

async def run_phase(self, phase):
async def main_phase(self, phase):
uvm_info(self.tag, f"Starting test {self.__class__.__name__}", UVM_LOW)
phase.raise_objection(self, f"{self.__class__.__name__} OBJECTED")
bus_gpio8_write_dir_seq = gpio8_write_dir_seq("gpio8_write_dir_seq")
bus_gpio8_write_dir_seq = gpio8_write_dir_seq("gpio8_write_dir_seq")
ip_gpio_set_io_in_seq = gpio8_set_io_in_seq("gpio8_set_io_in_seq")
bus_gpio8_write_dir_seq.set_gpios_dir(0) # set all IOs dir to input
bus_gpio8_write_dir_seq.set_gpios_dir(0) # set all IOs dir to input
ip_gpio_set_io_in_seq.set_gpios_dir(0)
bus_gpio8_write_im_seq = gpio8_write_im_seq("gpio8_write_im_seq")
bus_gpio8_write_ic_seq = gpio8_write_ic_seq("gpio8_write_ic_seq")
bus_gpio8_read_ris_seq = gpio8_read_ris_seq("gpio8_read_ris_seq")
bus_gpio8_read_mis_seq = gpio8_read_mis_seq("gpio8_read_mis_seq")

await bus_gpio8_write_dir_seq.start(
self.bus_sqr
) # set all IOs direction to input because interrupts are for input IOs

await bus_gpio8_write_dir_seq.start(self.bus_sqr) # set all IOs direction to input because interrupts are for input IOs

# IO is high
for i in range (8):
# IO is high
for i in range(8):
bus_gpio8_write_im_seq.set_im(1 << i)
ip_gpio_set_io_in_seq.set_gpios_in (1 << i)
bus_gpio8_write_ic_seq.set_ic (1 << i)
await bus_gpio8_write_im_seq.start( self.bus_sqr) # mask the interrupt
await ip_gpio_set_io_in_seq.start(self.ip_sqr) # set the IO
await bus_gpio8_read_ris_seq.start(self.bus_sqr) # read ris to check that it has the correct value
await bus_gpio8_read_mis_seq.start(self.bus_sqr) # read mis to check that it has the correct value
ip_gpio_set_io_in_seq.set_gpios_in (0x00) # set the IOs to low (to prevent the rising of the irq again)
await ip_gpio_set_io_in_seq.start(self.ip_sqr)
await bus_gpio8_write_ic_seq.start(self.bus_sqr) # clear the interrupt

# IO is low
ip_gpio_set_io_in_seq.set_gpios_in (0xFF) # set all IOs to low
await ip_gpio_set_io_in_seq.start(self.ip_sqr)
for i in range (8):
bus_gpio8_write_im_seq.set_im(1 << (i+8))
ip_gpio_set_io_in_seq.set_gpios_in (~(1 << i))
bus_gpio8_write_ic_seq.set_ic (1 << (i+8))
await bus_gpio8_write_im_seq.start( self.bus_sqr) # mask the interrupt
await ip_gpio_set_io_in_seq.start(self.ip_sqr) # clear IO i
await bus_gpio8_read_ris_seq.start(self.bus_sqr) # read ris to check that it has the correct value
await bus_gpio8_read_mis_seq.start(self.bus_sqr) # read mis to check that it has the correct value
ip_gpio_set_io_in_seq.set_gpios_in (1<<i) # set IO {i} to high (to preven the rising of the irq again)
await ip_gpio_set_io_in_seq.start(self.ip_sqr)
await bus_gpio8_write_ic_seq.start(self.bus_sqr) # clear the interrupt
ip_gpio_set_io_in_seq.set_gpios_in(1 << i)
bus_gpio8_write_ic_seq.set_ic(1 << i)
await bus_gpio8_write_im_seq.start(self.bus_sqr) # mask the interrupt
await ip_gpio_set_io_in_seq.start(self.ip_sqr) # set the IO
await bus_gpio8_read_ris_seq.start(
self.bus_sqr
) # read ris to check that it has the correct value
await bus_gpio8_read_mis_seq.start(
self.bus_sqr
) # read mis to check that it has the correct value
ip_gpio_set_io_in_seq.set_gpios_in(
0x00
) # set the IOs to low (to prevent the rising of the irq again)
await ip_gpio_set_io_in_seq.start(self.ip_sqr)
await bus_gpio8_write_ic_seq.start(self.bus_sqr) # clear the interrupt

# IO is low
ip_gpio_set_io_in_seq.set_gpios_in(0xFF) # set all IOs to low
await ip_gpio_set_io_in_seq.start(self.ip_sqr)
for i in range(8):
bus_gpio8_write_im_seq.set_im(1 << (i + 8))
ip_gpio_set_io_in_seq.set_gpios_in(~(1 << i))
bus_gpio8_write_ic_seq.set_ic(1 << (i + 8))
await bus_gpio8_write_im_seq.start(self.bus_sqr) # mask the interrupt
await ip_gpio_set_io_in_seq.start(self.ip_sqr) # clear IO i
await bus_gpio8_read_ris_seq.start(
self.bus_sqr
) # read ris to check that it has the correct value
await bus_gpio8_read_mis_seq.start(
self.bus_sqr
) # read mis to check that it has the correct value
ip_gpio_set_io_in_seq.set_gpios_in(
1 << i
) # set IO {i} to high (to preven the rising of the irq again)
await ip_gpio_set_io_in_seq.start(self.ip_sqr)
await bus_gpio8_write_ic_seq.start(self.bus_sqr) # clear the interrupt

# Positive Edge interrupts
ip_gpio_set_io_in_seq.set_gpios_in (0x00)
await ip_gpio_set_io_in_seq.start(self.ip_sqr) # set all IOs to low
for i in range (8):
bus_gpio8_write_im_seq.set_im(1 << (i+16))
ip_gpio_set_io_in_seq.set_gpios_in (1 << i)
bus_gpio8_write_ic_seq.set_ic (1 << (i+16))
await bus_gpio8_write_im_seq.start( self.bus_sqr) # mask the interrupt
await ip_gpio_set_io_in_seq.start(self.ip_sqr) # set the IO
await bus_gpio8_read_ris_seq.start(self.bus_sqr) # read ris to check that it has the correct value
await bus_gpio8_read_mis_seq.start(self.bus_sqr) # read mis to check that it has the correct value
await bus_gpio8_write_ic_seq.start(self.bus_sqr) # clear the interrupt
ip_gpio_set_io_in_seq.set_gpios_in(0x00)
await ip_gpio_set_io_in_seq.start(self.ip_sqr) # set all IOs to low
for i in range(8):
bus_gpio8_write_im_seq.set_im(1 << (i + 16))
ip_gpio_set_io_in_seq.set_gpios_in(1 << i)
bus_gpio8_write_ic_seq.set_ic(1 << (i + 16))
await bus_gpio8_write_im_seq.start(self.bus_sqr) # mask the interrupt
await ip_gpio_set_io_in_seq.start(self.ip_sqr) # set the IO
await bus_gpio8_read_ris_seq.start(
self.bus_sqr
) # read ris to check that it has the correct value
await bus_gpio8_read_mis_seq.start(
self.bus_sqr
) # read mis to check that it has the correct value
await bus_gpio8_write_ic_seq.start(self.bus_sqr) # clear the interrupt

# Negative edge interrupts
ip_gpio_set_io_in_seq.set_gpios_in (0xFF)
await ip_gpio_set_io_in_seq.start(self.ip_sqr) # set all IOs to high
for i in range (8):
gpios_in = 0xFF & ~(1 << i) # set IO {i} to low (to create a negative edge)
bus_gpio8_write_im_seq.set_im(1 << (i+24))
ip_gpio_set_io_in_seq.set_gpios_in (gpios_in)
bus_gpio8_write_ic_seq.set_ic (1 << (i+24))
await bus_gpio8_write_im_seq.start( self.bus_sqr) # mask the interrupt
await ip_gpio_set_io_in_seq.start(self.ip_sqr) # set the IO
await bus_gpio8_read_ris_seq.start(self.bus_sqr) # read ris to check that it has the correct value
await bus_gpio8_read_mis_seq.start(self.bus_sqr) # read mis to check that it has the correct value
await bus_gpio8_write_ic_seq.start(self.bus_sqr) # clear the interrupt


await Timer(1000 , "ns")
ip_gpio_set_io_in_seq.set_gpios_in(0xFF)
await ip_gpio_set_io_in_seq.start(self.ip_sqr) # set all IOs to high
for i in range(8):
gpios_in = 0xFF & ~(1 << i) # set IO {i} to low (to create a negative edge)
bus_gpio8_write_im_seq.set_im(1 << (i + 24))
ip_gpio_set_io_in_seq.set_gpios_in(gpios_in)
bus_gpio8_write_ic_seq.set_ic(1 << (i + 24))
await bus_gpio8_write_im_seq.start(self.bus_sqr) # mask the interrupt
await ip_gpio_set_io_in_seq.start(self.ip_sqr) # set the IO
await bus_gpio8_read_ris_seq.start(
self.bus_sqr
) # read ris to check that it has the correct value
await bus_gpio8_read_mis_seq.start(
self.bus_sqr
) # read mis to check that it has the correct value
await bus_gpio8_write_ic_seq.start(self.bus_sqr) # clear the interrupt

await Timer(1000, "ns")
phase.drop_objection(self, f"{self.__class__.__name__} drop objection")

uvm_component_utils(gpio8_interrupts_test)

uvm_component_utils(gpio8_interrupts_test)

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