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[RISC-V] Reverse changes from PR#111887 for riscv64 architecture #111951
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RISC-V Release-CLR-QEMU: 9451 / 9495 (99.54%)
Release-CLR-QEMU.md, Release-CLR-QEMU.xml, testclr_output.tar.gz RISC-V Release-FX-QEMU: 0 / 259 (0.00%)
Release-FX-QEMU.md, Release-FX-QEMU.xml, testfx_output.tar.gz Build information and commandsGIT: RISC-V Release-CLR-QEMU: 9462 / 9534 (99.24%)
Release-CLR-QEMU.md, Release-CLR-QEMU.xml, testclr_output.tar.gz RISC-V Release-FX-QEMU: 0 / 259 (0.00%)
Release-FX-QEMU.md, Release-FX-QEMU.xml, testfx_output.tar.gz Build information and commandsGIT: |
The tests are supposed to be disabled by different mechanism: runtime/src/tests/JIT/jit64/jit64_2.csproj Lines 2 to 4 in d9b7515
I wonder why that doesn't work for your use case. |
@filipnavara That's a good question, we don't know yet, it's a temporary solution created on the fly |
I've run multiple tests regarding this issue and it seems that the problem lies is elsewhere. Most of the failures we are getting right now in coreclr are related to segmentation faults. Therefore I'm closing this PR. |
We're building with BuildAllTestsAsStandalone, I made another attempt #112399 |
We haven't added support for vararg on riscv64 yet. Removing tests that needs vararg support from exclusion list (#111887) won't make them work, it will just show us more failures, that are related to unsupported functions.
When we add vararg support, we will re-enable these tests.
Before:
After:
Part of #84834, cc @dotnet/samsung