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[LoongArch64/RiscV] Add memory barriers to native AOT asm helpers #106219

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jkotas opened this issue Aug 10, 2024 · 2 comments
Open

[LoongArch64/RiscV] Add memory barriers to native AOT asm helpers #106219

jkotas opened this issue Aug 10, 2024 · 2 comments
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arch-loongarch64 arch-riscv Related to the RISC-V architecture area-NativeAOT-coreclr
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jkotas commented Aug 10, 2024

This issue tracks adding memory barrier to native AOT R2R asm helpers on LoongArch64 and RiscV

See #106004 for arm and arm64 of the change.
@jkotas jkotas added area-NativeAOT-coreclr arch-loongarch64 arch-riscv Related to the RISC-V architecture labels Aug 10, 2024
@jkotas jkotas added this to the Future milestone Aug 10, 2024
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Tagging subscribers to this area: @agocke, @MichalStrehovsky, @jkotas
See info in area-owners.md if you want to be subscribed.

@jkotas jkotas mentioned this issue Aug 10, 2024
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jkotas commented Aug 10, 2024

cc @dotnet/samsung @shushanhf @LuckyXu-HF

@jkotas jkotas changed the title [LoongArch64/RiscV] memory barriers to native AOT asm helpers [LoongArch64/RiscV] Add memory barriers to native AOT asm helpers Aug 10, 2024
@shushanhf shushanhf mentioned this issue Aug 12, 2024
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@filipnavara filipnavara mentioned this issue Feb 18, 2025
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filipnavara added a commit to am11/runtime that referenced this issue Feb 18, 2025
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WIP: Add memory barriers to native AOT asm helpers (dotnet#106219)
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arch-loongarch64 arch-riscv Related to the RISC-V architecture area-NativeAOT-coreclr
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