Add Parallel make for supported targets

Makefile

@@ -40,7 +40,7 @@ else
     export REDIR=>/dev/null
 endif
 
-PARALLEL ?= 0
+PARALLEL ?= 1
 ifeq ($(RISCV_TARGET),spike)
 	PARALLEL = 0
 endif
@@ -49,8 +49,6 @@ ifeq ($(PARALLEL),0)
 else
     ifeq ($(RISCV_TARGET),riscvOVPsim)
         JOBS ?= -j8 --max-load=4
-    else
-        JOBS ?= -j4 --max-load=2
     endif
 endif
 

riscv-target/riscvOVPsim/compliance_io.h

@@ -51,24 +51,34 @@
 
 #else
 
-#define RSIZE 4
+#if (__riscv_xlen==32)
+#    define RSIZE 4
+#    define SX sw
+#    define LX lw
+#endif
+#if (__riscv_xlen==64)
+#    define RSIZE 8
+#    define SX sd
+#    define LX ld
+#endif
+
 // _SP = (volatile register)
 #define LOCAL_IO_PUSH(_SP)                                              \
     la      _SP,  begin_regstate;                                       \
-    sw      x1,   (1*RSIZE)(_SP);                                       \
-    sw      x5,   (5*RSIZE)(_SP);                                       \
-    sw      x6,   (6*RSIZE)(_SP);                                       \
-    sw      x8,   (8*RSIZE)(_SP);                                       \
-    sw      x10,  (10*RSIZE)(_SP);
+    SX      x1,   (1*RSIZE)(_SP);                                       \
+    SX      x5,   (5*RSIZE)(_SP);                                       \
+    SX      x6,   (6*RSIZE)(_SP);                                       \
+    SX      x8,   (8*RSIZE)(_SP);                                       \
+    SX      x10,  (10*RSIZE)(_SP);
 
 // _SP = (volatile register)
 #define LOCAL_IO_POP(_SP)                                               \
     la      _SP,   begin_regstate;                                      \
-    lw      x1,   (1*RSIZE)(_SP);                                       \
-    lw      x5,   (5*RSIZE)(_SP);                                       \
-    lw      x6,   (6*RSIZE)(_SP);                                       \
-    lw      x8,   (8*RSIZE)(_SP);                                       \
-    lw      x10,  (10*RSIZE)(_SP);
+    LX      x1,   (1*RSIZE)(_SP);                                       \
+    LX      x5,   (5*RSIZE)(_SP);                                       \
+    LX      x6,   (6*RSIZE)(_SP);                                       \
+    LX      x8,   (8*RSIZE)(_SP);                                       \
+    LX      x10,  (10*RSIZE)(_SP);
 
 #define LOCAL_IO_WRITE_GPR(_R)                                          \
     mv          a0, _R;                                                 \

riscv-target/riscvOVPsim/compliance_test.h

@@ -17,7 +17,10 @@
         RVTEST_PASS                                                           \
 
 #define RV_COMPLIANCE_RV32M                                                   \
-        RVTEST_RV32M                                                          \
+        RVTEST_RV32M       
+
+#define RV_COMPLIANCE_RV64V                                                  \
+        RVTEST_RV64V                                                          \
 
 #define RV_COMPLIANCE_CODE_BEGIN                                              \
         RVTEST_CODE_BEGIN                                                     \

riscv-target/riscvOVPsim/device/rv32Zicsr/Makefile.include

@@ -12,29 +12,31 @@ endif
 
 RUN_TARGET=\
     $(TARGET_SIM) $(TARGET_FLAGS) \
-        --variant RV32I --program $(work_dir_isa)/$< \
+        --variant RV32I --program $(<) \
         --signaturedump --customcontrol \
-        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*).signature.output \
+        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(*).signature.output \
         --override riscvOVPsim/cpu/sigdump/ResultReg=3 \
         --override riscvOVPsim/cpu/simulateexceptions=T \
         --override riscvOVPsim/cpu/defaultsemihost=F \
-        --logfile $(work_dir_isa)/$@ \
+        --logfile $(@) \
         --override riscvOVPsim/cpu/user_version=2.3 \
-        --override riscvOVPsim/cpu/priv_version=1.11; \
-				cat $(work_dir_isa)/$(*).signature.output | sed 's/.\{8\}/& /g' | \
-				awk '{print $$4 " " $$3 " " $$2 " " $$1}' | sed 's/ /\n/g' > temp; \
-				mv temp $(work_dir_isa)/$(*).signature.output;
+        --override riscvOVPsim/cpu/priv_version=1.11 $(REDIR); \
+            cat $(*).signature.output | \
+            sed 's/.\{8\}/& /g' | \
+            awk '{print $$4 " " $$3 " " $$2 " " $$1}' | \
+            sed 's/ /\n/g' > $(*).temp; \
+            mv $(*).temp $(*).signature.output;
 
 RISCV_PREFIX   ?= riscv32-unknown-elf-
 RISCV_GCC      ?= $(RISCV_PREFIX)gcc
 RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
 RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
 
 COMPILE_TARGET=\
-	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \
-		-I$(ROOTDIR)/riscv-test-env/ \
-		-I$(ROOTDIR)/riscv-test-env/p/ \
-		-I$(TARGETDIR)/$(RISCV_TARGET)/ \
-		-T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \
-		-o $(work_dir_isa)/$$@; \
-	$$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump
+    $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+        -I$(ROOTDIR)/riscv-test-env/ \
+        -I$(ROOTDIR)/riscv-test-env/p/ \
+        -I$(TARGETDIR)/$(RISCV_TARGET)/ \
+        -T$(ROOTDIR)/riscv-test-env/p/link.ld $$(<) \
+        -o $$(@); \
+    $$(RISCV_OBJDUMP) -D $$(@) > $$(@).objdump

riscv-target/riscvOVPsim/device/rv32Zifencei/Makefile.include

@@ -12,29 +12,31 @@ endif
 
 RUN_TARGET=\
     $(TARGET_SIM) $(TARGET_FLAGS) \
-        --variant RV32I --program $(work_dir_isa)/$< \
+        --variant RV32I --program $(<) \
         --signaturedump --customcontrol \
-        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*).signature.output \
+        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(*).signature.output \
         --override riscvOVPsim/cpu/sigdump/ResultReg=3 \
         --override riscvOVPsim/cpu/simulateexceptions=T \
         --override riscvOVPsim/cpu/defaultsemihost=F \
-        --logfile $(work_dir_isa)/$@ \
+        --logfile $(@) \
         --override riscvOVPsim/cpu/user_version=2.3 \
-        --override riscvOVPsim/cpu/priv_version=1.11; \
-				cat $(work_dir_isa)/$(*).signature.output | sed 's/.\{8\}/& /g' | \
-				awk '{print $$4 " " $$3 " " $$2 " " $$1}' | sed 's/ /\n/g' > temp; \
-				mv temp $(work_dir_isa)/$(*).signature.output;
+        --override riscvOVPsim/cpu/priv_version=1.11 $(REDIR); \
+            cat $(*).signature.output | \
+            sed 's/.\{8\}/& /g' | \
+            awk '{print $$4 " " $$3 " " $$2 " " $$1}' | \
+            sed 's/ /\n/g' > $(*).temp; \
+            mv $(*).temp $(*).signature.output;
 
 RISCV_PREFIX   ?= riscv32-unknown-elf-
 RISCV_GCC      ?= $(RISCV_PREFIX)gcc
 RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
 RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
 
 COMPILE_TARGET=\
-	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \
-		-I$(ROOTDIR)/riscv-test-env/ \
-		-I$(ROOTDIR)/riscv-test-env/p/ \
-		-I$(TARGETDIR)/$(RISCV_TARGET)/ \
-		-T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \
-		-o $(work_dir_isa)/$$@; \
-	$$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump
+    $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+        -I$(ROOTDIR)/riscv-test-env/ \
+        -I$(ROOTDIR)/riscv-test-env/p/ \
+        -I$(TARGETDIR)/$(RISCV_TARGET)/ \
+        -T$(ROOTDIR)/riscv-test-env/p/link.ld $$(<) \
+        -o $$(@); \
+    $$(RISCV_OBJDUMP) -D $$(@) > $$(@).objdump

riscv-target/riscvOVPsim/device/rv32i/Makefile.include

@@ -12,29 +12,31 @@ endif
 
 RUN_TARGET=\
     $(TARGET_SIM) $(TARGET_FLAGS) \
-        --variant RV32I --program $(work_dir_isa)/$< \
+        --variant RV32I --program $(<) \
         --signaturedump --customcontrol \
-        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*).signature.output \
+        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(*).signature.output \
         --override riscvOVPsim/cpu/sigdump/ResultReg=3 \
         --override riscvOVPsim/cpu/simulateexceptions=T \
         --override riscvOVPsim/cpu/defaultsemihost=F \
-        --logfile $(work_dir_isa)/$@ \
+        --logfile $(@) \
         --override riscvOVPsim/cpu/user_version=2.3 \
-        --override riscvOVPsim/cpu/priv_version=1.11; \
-				cat $(work_dir_isa)/$(*).signature.output | sed 's/.\{8\}/& /g' | \
-				awk '{print $$4 " " $$3 " " $$2 " " $$1}' | sed 's/ /\n/g' > temp; \
-				mv temp $(work_dir_isa)/$(*).signature.output;
+        --override riscvOVPsim/cpu/priv_version=1.11 $(REDIR); \
+            cat $(*).signature.output | \
+            sed 's/.\{8\}/& /g' | \
+            awk '{print $$4 " " $$3 " " $$2 " " $$1}' | \
+            sed 's/ /\n/g' > $(*).temp; \
+            mv $(*).temp $(*).signature.output;
 
 RISCV_PREFIX   ?= riscv32-unknown-elf-
 RISCV_GCC      ?= $(RISCV_PREFIX)gcc
 RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
 RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
 
 COMPILE_TARGET=\
-	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \
-		-I$(ROOTDIR)/riscv-test-env/ \
-		-I$(ROOTDIR)/riscv-test-env/p/ \
-		-I$(TARGETDIR)/$(RISCV_TARGET)/ \
-		-T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \
-		-o $(work_dir_isa)/$$@; \
-	$$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump
+    $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+        -I$(ROOTDIR)/riscv-test-env/ \
+        -I$(ROOTDIR)/riscv-test-env/p/ \
+        -I$(TARGETDIR)/$(RISCV_TARGET)/ \
+        -T$(ROOTDIR)/riscv-test-env/p/link.ld $$(<) \
+        -o $$(@); \
+    $$(RISCV_OBJDUMP) -D $$(@) > $$(@).objdump

riscv-target/riscvOVPsim/device/rv32im/Makefile.include

@@ -12,30 +12,31 @@ endif
 
 RUN_TARGET=\
     $(TARGET_SIM) $(TARGET_FLAGS) \
-        --variant RV32IM --program $(work_dir_isa)/$< \
+        --variant RV32IM --program $(<) \
         --signaturedump --customcontrol \
-        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*).signature.output \
+        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(*).signature.output \
         --override riscvOVPsim/cpu/sigdump/ResultReg=3 \
         --override riscvOVPsim/cpu/simulateexceptions=T \
         --override riscvOVPsim/cpu/defaultsemihost=F \
-        --logfile $(work_dir_isa)/$@ \
+        --logfile $(@) \
         --override riscvOVPsim/cpu/user_version=2.3 \
-        --override riscvOVPsim/cpu/priv_version=1.11; \
-				cat $(work_dir_isa)/$(*).signature.output | sed 's/.\{8\}/& /g' | \
-				awk '{print $$4 " " $$3 " " $$2 " " $$1}' | sed 's/ /\n/g' > temp; \
-				mv temp $(work_dir_isa)/$(*).signature.output;
-
+        --override riscvOVPsim/cpu/priv_version=1.11 $(REDIR); \
+            cat $(*).signature.output | \
+            sed 's/.\{8\}/& /g' | \
+            awk '{print $$4 " " $$3 " " $$2 " " $$1}' | \
+            sed 's/ /\n/g' > $(*).temp; \
+            mv $(*).temp $(*).signature.output;
 
 RISCV_PREFIX   ?= riscv32-unknown-elf-
 RISCV_GCC      ?= $(RISCV_PREFIX)gcc
 RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
 RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
 
 COMPILE_TARGET=\
-	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \
-		-I$(ROOTDIR)/riscv-test-env/ \
-		-I$(ROOTDIR)/riscv-test-env/p/ \
-		-I$(TARGETDIR)/$(RISCV_TARGET)/ \
-		-T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \
-		-o $(work_dir_isa)/$$@; \
-	$$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump
+    $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+        -I$(ROOTDIR)/riscv-test-env/ \
+        -I$(ROOTDIR)/riscv-test-env/p/ \
+        -I$(TARGETDIR)/$(RISCV_TARGET)/ \
+        -T$(ROOTDIR)/riscv-test-env/p/link.ld $$(<) \
+        -o $$(@); \
+    $$(RISCV_OBJDUMP) -D $$(@) > $$(@).objdump

riscv-target/riscvOVPsim/device/rv32imc/Makefile.include

@@ -12,32 +12,31 @@ endif
 
 RUN_TARGET=\
     $(TARGET_SIM) $(TARGET_FLAGS) \
-        --variant RV32IMC --program $(work_dir_isa)/$< \
+        --variant RV32IMC --program $(<) \
         --signaturedump --customcontrol \
-        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*).signature.output \
+        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(*).signature.output \
         --override riscvOVPsim/cpu/sigdump/ResultReg=3 \
         --override riscvOVPsim/cpu/simulateexceptions=T \
         --override riscvOVPsim/cpu/defaultsemihost=F \
-        --logfile $(work_dir_isa)/$@ \
+        --logfile $(@) \
         --override riscvOVPsim/cpu/user_version=2.3 \
-        --override riscvOVPsim/cpu/priv_version=1.11; \
-				cat $(work_dir_isa)/$(*).signature.output | sed 's/.\{8\}/& /g' | \
-				awk '{print $$4 " " $$3 " " $$2 " " $$1}' | sed 's/ /\n/g' > temp; \
-				mv temp $(work_dir_isa)/$(*).signature.output;
+        --override riscvOVPsim/cpu/priv_version=1.11 $(REDIR); \
+            cat $(*).signature.output | \
+            sed 's/.\{8\}/& /g' | \
+            awk '{print $$4 " " $$3 " " $$2 " " $$1}' | \
+            sed 's/ /\n/g' > $(*).temp; \
+            mv $(*).temp $(*).signature.output;
 
 RISCV_PREFIX   ?= riscv32-unknown-elf-
 RISCV_GCC      ?= $(RISCV_PREFIX)gcc
 RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
-RISCV_NM       ?= $(RISCV_PREFIX)nm
 RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
 
 COMPILE_TARGET=\
-	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \
-		-I$(ROOTDIR)/riscv-test-env/ \
-		-I$(ROOTDIR)/riscv-test-env/p/ \
-		-I$(TARGETDIR)/$(RISCV_TARGET)/ \
-		-T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \
-		-o $(work_dir_isa)/$$@; \
-    $$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump; \
-    $$(RISCV_NM) -a -n $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.nm;
-
+    $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+        -I$(ROOTDIR)/riscv-test-env/ \
+        -I$(ROOTDIR)/riscv-test-env/p/ \
+        -I$(TARGETDIR)/$(RISCV_TARGET)/ \
+        -T$(ROOTDIR)/riscv-test-env/p/link.ld $$(<) \
+        -o $$(@); \
+    $$(RISCV_OBJDUMP) -D $$(@) > $$(@).objdump

riscv-target/riscvOVPsim/device/rv32mi/Makefile.include

@@ -12,29 +12,31 @@ endif
 
 RUN_TARGET=\
     $(TARGET_SIM) $(TARGET_FLAGS) \
-        --variant RV32I --program $(work_dir_isa)/$< \
+        --variant RV32I --program $(<) \
         --signaturedump --customcontrol \
-        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(work_dir_isa)/$(*).signature.output \
+        --override riscvOVPsim/cpu/sigdump/SignatureFile=$(*).signature.output \
         --override riscvOVPsim/cpu/sigdump/ResultReg=3 \
         --override riscvOVPsim/cpu/simulateexceptions=T \
         --override riscvOVPsim/cpu/defaultsemihost=F \
-        --logfile $(work_dir_isa)/$@ \
-        --override riscvOVPsim/cpu/user_version=2.2 \
-        --override riscvOVPsim/cpu/priv_version=1.10; \
-				cat $(work_dir_isa)/$(*).signature.output | sed 's/.\{8\}/& /g' | \
-				awk '{print $$4 " " $$3 " " $$2 " " $$1}' | sed 's/ /\n/g' > temp; \
-				mv temp $(work_dir_isa)/$(*).signature.output;
+        --logfile $(@) \
+        --override riscvOVPsim/cpu/user_version=2.3 \
+        --override riscvOVPsim/cpu/priv_version=1.11 $(REDIR); \
+            cat $(*).signature.output | \
+            sed 's/.\{8\}/& /g' | \
+            awk '{print $$4 " " $$3 " " $$2 " " $$1}' | \
+            sed 's/ /\n/g' > $(*).temp; \
+            mv $(*).temp $(*).signature.output;
 
 RISCV_PREFIX   ?= riscv32-unknown-elf-
 RISCV_GCC      ?= $(RISCV_PREFIX)gcc
 RISCV_OBJDUMP  ?= $(RISCV_PREFIX)objdump
 RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
 
 COMPILE_TARGET=\
-	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \
-		-I$(ROOTDIR)/riscv-test-env/ \
-		-I$(ROOTDIR)/riscv-test-env/p/ \
-		-I$(TARGETDIR)/$(RISCV_TARGET)/ \
-		-T$(ROOTDIR)/riscv-test-env/p/link.ld $$< \
-		-o $(work_dir_isa)/$$@; \
-	$$(RISCV_OBJDUMP) -D $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump
+    $$(RISCV_GCC) $(1) $$(RISCV_GCC_OPTS) \
+        -I$(ROOTDIR)/riscv-test-env/ \
+        -I$(ROOTDIR)/riscv-test-env/p/ \
+        -I$(TARGETDIR)/$(RISCV_TARGET)/ \
+        -T$(ROOTDIR)/riscv-test-env/p/link.ld $$(<) \
+        -o $$(@); \
+    $$(RISCV_OBJDUMP) -D $$(@) > $$(@).objdump