Add Load Register Subset Operation

chip8/cpu.py

@@ -258,6 +258,8 @@ def misc_routines(self):
         sub_operation = self.operand & 0x000F
         if sub_operation == 0x2:
             self.store_subset_regs_in_memory()
+        elif sub_operation == 0x3:
+            self.read_subset_regs_in_memory()
         else:
             try:
                 self.misc_routine_lookup[operation]()
@@ -867,6 +869,32 @@ def store_subset_regs_in_memory(self):
 
         self.last_op = f"STORSUB [I], {x:01X}, {y:01X}"
 
+    def read_subset_regs_in_memory(self):
+        """
+        Fxy3 - LOADSUB [I], Vx, Vy
+
+        Load a subset of registers from x to y in memory starting at index.
+        The x and y calculation is as follows:
+
+           Bits:  15-12     11-8      7-4       3-0
+                    F         x        y         2
+
+        If x is larger than y, then they will be loaded in reverse order.
+        """
+        x = (self.operand & 0x0F00) >> 8
+        y = (self.operand & 0x00F0) >> 4
+        pointer = 0
+        if y >= x:
+            for z in range(x, y+1):
+                self.v[z] = self.memory[self.index + pointer]
+                pointer += 1
+        else:
+            for z in range(x, y-1, -1):
+                self.v[z] = self.memory[self.index + pointer]
+                pointer += 1
+
+        self.last_op = f"LOADSUB [I], {x:01X}, {y:01X}"
+
     def move_delay_timer_into_reg(self):
         """
         Fx07 - LOAD Vx, DELAY

test/test_chip8cpu.py

@@ -955,6 +955,57 @@ def test_store_subset_regs_integration(self):
         self.assertEqual(6, self.cpu.memory[0x5001])
         self.assertEqual(5, self.cpu.memory[0x5002])
 
+    def test_readsubset_regs_one_two(self):
+        self.cpu.v[1] = 5
+        self.cpu.v[2] = 6
+        self.cpu.index = 0x5000
+        self.cpu.operand = 0xF123
+        self.cpu.memory[0x5000] = 7
+        self.cpu.memory[0x5001] = 8
+        self.cpu.read_subset_regs_in_memory()
+        self.assertEqual(7, self.cpu.v[1])
+        self.assertEqual(8, self.cpu.v[2])
+
+    def test_read_subset_regs_one_one(self):
+        self.cpu.v[1] = 5
+        self.cpu.v[2] = 6
+        self.cpu.index = 0x5000
+        self.cpu.operand = 0xF113
+        self.cpu.memory[0x5000] = 7
+        self.cpu.memory[0x5001] = 8
+        self.cpu.read_subset_regs_in_memory()
+        self.assertEqual(7, self.cpu.v[1])
+        self.assertEqual(6, self.cpu.v[2])
+
+    def test_read_subset_regs_three_one(self):
+        self.cpu.v[1] = 5
+        self.cpu.v[2] = 6
+        self.cpu.v[3] = 7
+        self.cpu.index = 0x5000
+        self.cpu.operand = 0xF313
+        self.cpu.memory[0x5000] = 8
+        self.cpu.memory[0x5001] = 9
+        self.cpu.memory[0x5002] = 10
+        self.cpu.read_subset_regs_in_memory()
+        self.assertEqual(10, self.cpu.v[1])
+        self.assertEqual(9, self.cpu.v[2])
+        self.assertEqual(8, self.cpu.v[3])
+
+    def test_read_subset_regs_integration(self):
+        self.cpu.v[1] = 5
+        self.cpu.v[2] = 6
+        self.cpu.v[3] = 7
+        self.cpu.index = 0x5000
+        self.cpu.memory[0x0200] = 0xF3
+        self.cpu.memory[0x0201] = 0x13
+        self.cpu.memory[0x5000] = 8
+        self.cpu.memory[0x5001] = 9
+        self.cpu.memory[0x5002] = 10
+        self.cpu.execute_instruction()
+        self.assertEqual(10, self.cpu.v[1])
+        self.assertEqual(9, self.cpu.v[2])
+        self.assertEqual(8, self.cpu.v[3])
+
 # M A I N #####################################################################