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fix test-payload build fail
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Signed-off-by: Ouyang, Hang <hang.ouyang@intel.com>
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OuyangHang33 authored and jyao1 committed Jun 20, 2024
1 parent feea45c commit dc1f02f
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Showing 7 changed files with 57 additions and 23 deletions.
3 changes: 2 additions & 1 deletion doc/test_with_td_payload.md
Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,8 @@ The output file **final.test.bin** with [test.json](../tests/test-td-payload/src
"attributes": 0,
"max_vcpus": 1,
"num_vcpus": 1,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": true
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12 changes: 8 additions & 4 deletions tests/test-td-payload/config/test_config_1.json
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,8 @@
"attributes": 0,
"max_vcpus": 1,
"num_vcpus": 1,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": true
Expand All @@ -16,7 +17,8 @@
"attributes": 0,
"max_vcpus": 2,
"num_vcpus": 2,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": false
Expand All @@ -27,7 +29,8 @@
"attributes": 0,
"max_vcpus": 4,
"num_vcpus": 4,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": false
Expand All @@ -38,7 +41,8 @@
"attributes": 0,
"max_vcpus": 8,
"num_vcpus": 8,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": false
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12 changes: 8 additions & 4 deletions tests/test-td-payload/config/test_config_2.json
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,8 @@
"attributes": 0,
"max_vcpus": 1,
"num_vcpus": 1,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": true
Expand All @@ -16,7 +17,8 @@
"attributes": 0,
"max_vcpus": 2,
"num_vcpus": 2,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": false
Expand All @@ -27,7 +29,8 @@
"attributes": 0,
"max_vcpus": 4,
"num_vcpus": 4,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": false
Expand All @@ -38,7 +41,8 @@
"attributes": 0,
"max_vcpus": 8,
"num_vcpus": 8,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": false
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12 changes: 8 additions & 4 deletions tests/test-td-payload/config/test_config_3.json
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,8 @@
"attributes": 0,
"max_vcpus": 1,
"num_vcpus": 1,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": false
Expand All @@ -16,7 +17,8 @@
"attributes": 0,
"max_vcpus": 2,
"num_vcpus": 2,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": true
Expand All @@ -27,7 +29,8 @@
"attributes": 0,
"max_vcpus": 4,
"num_vcpus": 4,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": false
Expand All @@ -38,7 +41,8 @@
"attributes": 0,
"max_vcpus": 8,
"num_vcpus": 8,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": false
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12 changes: 8 additions & 4 deletions tests/test-td-payload/config/test_config_4.json
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,8 @@
"attributes": 0,
"max_vcpus": 1,
"num_vcpus": 1,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": false
Expand All @@ -16,7 +17,8 @@
"attributes": 0,
"max_vcpus": 2,
"num_vcpus": 2,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": false
Expand All @@ -27,7 +29,8 @@
"attributes": 0,
"max_vcpus": 4,
"num_vcpus": 4,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": true
Expand All @@ -38,7 +41,8 @@
"attributes": 0,
"max_vcpus": 8,
"num_vcpus": 8,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": false
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12 changes: 8 additions & 4 deletions tests/test-td-payload/config/test_config_5.json
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,8 @@
"attributes": 0,
"max_vcpus": 1,
"num_vcpus": 1,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": false
Expand All @@ -16,7 +17,8 @@
"attributes": 0,
"max_vcpus": 2,
"num_vcpus": 2,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": false
Expand All @@ -27,7 +29,8 @@
"attributes": 0,
"max_vcpus": 4,
"num_vcpus": 4,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": false
Expand All @@ -38,7 +41,8 @@
"attributes": 0,
"max_vcpus": 8,
"num_vcpus": 8,
"rsvd": [0,0,0]
"vcpu_index":0,
"rsvd": [0,0,0,0,0]
},
"result": "None",
"run": true
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17 changes: 15 additions & 2 deletions tests/test-td-payload/src/testtdinfo.rs
Original file line number Diff line number Diff line change
Expand Up @@ -18,15 +18,17 @@ pub struct TdInfoRetData {
pub attributes: u64,
pub max_vcpus: u32,
pub num_vcpus: u32,
pub rsvd: [u64; 3],
pub vcpu_index: u32,
pub rsvd: [u32; 5],
}

#[derive(Debug, Serialize, Deserialize)]
pub struct TdInfoExpectedData {
pub attributes: u64,
pub max_vcpus: u32,
pub num_vcpus: u32,
pub rsvd: [u64; 3],
pub vcpu_index: u32,
pub rsvd: [u32; 5],
}

/**
Expand Down Expand Up @@ -98,6 +100,17 @@ impl TestCase for Tdinfo {
return;
}

if (self.expected.vcpu_index != td_info.vcpu_index) {
log::info!(
"Check vcpu_index fail - Expected {:?}: Actual {:?}\n",
self.expected.vcpu_index,
td_info.vcpu_index
);
return;
} else {
log::info!("vcpu_index - {:?}\n", td_info.vcpu_index);
}

if (self.expected.rsvd != td_info.rsvd) {
log::info!(
"Check rsvd fail - Expected {:?}: Actual {:?}\n",
Expand Down

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