Make x00x more intercompatible with v003, this makes it so x00x proje…

…cts can be built without v003 shims.

ch32fun/ch32fun.c

@@ -984,7 +984,7 @@ void InterruptVectorDefault( void )
 #endif
 }
 
-#if defined( CH32V003 ) || defined( CH32X03x )
+#if defined( CH32V003 ) || defined( CH32X03x ) || defined(CH32V00x)
 
 void handle_reset( void )
 {
@@ -1467,7 +1467,7 @@ WEAK int putchar(int c)
 
 void DelaySysTick( uint32_t n )
 {
-#ifdef CH32V003
+#if defined(CH32V003) || defined(CH32V00x)
 	uint32_t targend = SysTick->CNT + n;
 	while( ((int32_t)( SysTick->CNT - targend )) < 0 );
 #elif defined(CH32V20x) || defined(CH32V30x)
@@ -1500,15 +1500,15 @@ void SystemInit( void )
 #endif
 
 #if defined(FUNCONF_USE_PLL) && FUNCONF_USE_PLL
-	#if defined(CH32V003)
+	#if defined(CH32V003) || defined(CH32V00x)
 		#define BASE_CFGR0 RCC_HPRE_DIV1 | RCC_PLLSRC_HSI_Mul2    // HCLK = SYSCLK = APB1 And, enable PLL
 	#elif defined(CH32V20x_D8W)
 		#define BASE_CFGR0 RCC_HPRE_DIV1 | RCC_PPRE2_DIV1 | RCC_PPRE1_DIV1 | PLL_MULTIPLICATION
 	#else
 		#define BASE_CFGR0 RCC_HPRE_DIV1 | RCC_PPRE2_DIV1 | RCC_PPRE1_DIV2 | PLL_MULTIPLICATION
 	#endif
 #else
-	#if defined(CH32V003) || defined(CH32X03x)
+	#if defined(CH32V003) || defined(CH32X03x) || defined(CH32V00x)
 		#define BASE_CFGR0 RCC_HPRE_DIV1     					  // HCLK = SYSCLK = APB1 And, no pll.
 	#else
 		#define BASE_CFGR0 RCC_HPRE_DIV1 | RCC_PPRE2_DIV1 | RCC_PPRE1_DIV1
@@ -1553,7 +1553,7 @@ void SystemInit( void )
 
 #elif defined(FUNCONF_USE_HSE) && FUNCONF_USE_HSE
 
-	#if defined(CH32V003)
+	#if defined(CH32V003) || defined(CH32V00x)
 		RCC->CTLR = BASE_CTLR | RCC_HSION | RCC_HSEON ;       		  // Keep HSI on while turning on HSE
 	#else
 		RCC->CTLR = RCC_HSEON;							  			  // Only turn on HSE.
@@ -1562,7 +1562,7 @@ void SystemInit( void )
 	// Values lifted from the EVT.  There is little to no documentation on what this does.
 	while(!(RCC->CTLR&RCC_HSERDY)) {};
 
-	#if defined(CH32V003)
+	#if defined(CH32V003) || defined(CH32V00x)
 		RCC->CFGR0 = RCC_PLLSRC_HSE_Mul2 | RCC_SW_HSE;
 	#else
 		RCC->CFGR0 = BASE_CFGR0 | RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE;
@@ -1631,12 +1631,12 @@ void funAnalogInit( void )
 	ADC1->CTLR2 |= ADC_ADON | ADC_EXTSEL;	// turn on ADC and set rule group to sw trig
 
 	// Reset calibration
-	ADC1->CTLR2 |= ADC_RSTCAL;
-	while(ADC1->CTLR2 & ADC_RSTCAL);
+	ADC1->CTLR2 |= CTLR2_RSTCAL_Set;
+	while(ADC1->CTLR2 & CTLR2_RSTCAL_Set);
 
 	// Calibrate
-	ADC1->CTLR2 |= ADC_CAL;
-	while(ADC1->CTLR2 & ADC_CAL);
+	ADC1->CTLR2 |= CTLR2_CAL_Set;
+	while(ADC1->CTLR2 & CTLR2_CAL_Set);
 
 }
 

ch32fun/ch32fun.h

@@ -338,6 +338,8 @@ typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
 
 #ifdef CH32V003
 	#include "ch32v003hw.h"
+#elif defined( CH32V002 ) || defined( CH32V004 ) || defined( CH32V005 ) || defined( CH32V006 )
+	#include "ch32x00xhw.h"
 #elif defined( CH32X03x )
 	#include "ch32x03xhw.h"
 #elif defined( CH32X03x )

ch32fun/ch32x00xhw.h

@@ -1,8 +1,8 @@
 /* This file supports the CH32V00X and CH32M00X family of chips
 */
 
-#ifndef TODO_HARDWARE_H
-#define TODO_HARDWARE_H
+#ifndef TODO_CH32X00X_H
+#define TODO_CH32X00X_H
 
 #include "ch32fun.h"
 
@@ -117,13 +117,19 @@ typedef struct
 #define HSE_Value             HSE_VALUE
 #define HSEStartUp_TimeOut    HSE_STARTUP_TIMEOUT
 
+// Datasheet recommends HSE of 24M
+#ifndef HSE_VALUE
+#define HSE_VALUE 24000000
+#endif
+
 #ifndef __ASSEMBLER__
 /* Analog to Digital Converter */
 typedef struct
 {
     __IO uint32_t STATR;
     __IO uint32_t CTLR1;
     __IO uint32_t CTLR2;
+    __IO uint32_t SAMPTR1;
     __IO uint32_t SAMPTR2;
     __IO uint32_t IOFR1;
     __IO uint32_t IOFR2;
@@ -235,6 +241,21 @@ typedef enum
 	GPIO_CFGLR_OUT_OD    = 0b0101,
 	GPIO_CFGLR_OUT_AF_PP = 0b1001,
 	GPIO_CFGLR_OUT_AF_OD = 0b1101,
+
+
+	// For intercompatibility with 003 legacy code.
+	GPIO_CFGLR_OUT_10Mhz_PP = 0b0001,
+	GPIO_CFGLR_OUT_2Mhz_PP = 0b0001,
+	GPIO_CFGLR_OUT_50Mhz_PP = 0b0001,
+	GPIO_CFGLR_OUT_10Mhz_OD = 0b0101,
+	GPIO_CFGLR_OUT_2Mhz_OD = 0b0101,
+	GPIO_CFGLR_OUT_50Mhz_OD = 0b0101,
+	GPIO_CFGLR_OUT_10Mhz_AF_PP = 0b1001,
+	GPIO_CFGLR_OUT_2Mhz_AF_PP = 0b1001,
+	GPIO_CFGLR_OUT_50Mhz_AF_PP = 0b1001,
+	GPIO_CFGLR_OUT_10Mhz_AF_OD = 0b1101,
+	GPIO_CFGLR_OUT_2Mhz_AF_OD = 0b1101,
+	GPIO_CFGLR_OUT_50Mhz_AF_OD = 0b1101,
 } GPIO_CFGLR_PIN_MODE_Typedef;
 
 /*  This was correct in the 003, but the 00X have 0b0010 as a reserved bit in this field.  The above enum never sets this bit as directed by the RM.  But it's included in the following structure as a 4 bit field becaus changing it to two disjoint bit fields would make life too painful.  */
@@ -403,11 +424,23 @@ typedef struct
     __IO uint32_t CTLR;
     __IO uint32_t CFGR0;
     __IO uint32_t INTR;
-    __IO uint32_t PB2PRSTR;
+	union
+	{
+	    __IO uint32_t PB2PRSTR;
+	    __IO uint32_t APB2PRSTR; // For 003 compatibility
+	};
     __IO uint32_t PB1PRSTR;
     __IO uint32_t HBPCENR;
-    __IO uint32_t PB2PCENR;
-    __IO uint32_t PB1PCENR;
+	union
+	{
+	    __IO uint32_t PB2PCENR;
+	    __IO uint32_t APB2PCENR; // For 003 compatibility
+	};
+	union
+	{
+	    __IO uint32_t PB1PCENR;
+	    __IO uint32_t APB1PCENR; // For 003 compatibility
+	};
     __IO uint32_t RESERVED0;
 	  __IO uint32_t RSTSCKR;
 } RCC_TypeDef;
@@ -1893,6 +1926,10 @@ typedef struct
 
 #define RCC_PLLSRC                              ((uint32_t)0x00010000) /* PLL entry clock source */
 
+//For compatibility with the v003
+#define RCC_PLLSRC_HSI_Mul2                     ((uint32_t)0x00000000) /* HSI clock*2 selected as PLL entry clock source */
+#define RCC_PLLSRC_HSE_Mul2                     ((uint32_t)0x00010000) /* HSE clock*2 selected as PLL entry clock source */
+
 #define RCC_CFGR0_MCO                           ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */
 #define RCC_MCO_0                               ((uint32_t)0x01000000) /* Bit 0 */
 #define RCC_MCO_1                               ((uint32_t)0x02000000) /* Bit 1 */