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asm: cleanups for v4 ISA #1214

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merged 6 commits into from
Nov 8, 2023
Merged

asm: cleanups for v4 ISA #1214

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d184704
asm: rename SMov to MovSX
lmb Nov 8, 2023
84862e8
asm: return an error when extended opcodes have offset
lmb Nov 8, 2023
9450fc3
asm: make extended ALUOp easier to understand
lmb Nov 8, 2023
2b6e4c4
asm: correct jumpMask
lmb Nov 8, 2023
4cac574
asm: fix OpCode doc comment
lmb Nov 8, 2023
712458c
asm: refuse marshaling unknown extended opcodes
lmb Nov 8, 2023
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20 changes: 10 additions & 10 deletions asm/alu.go
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Original file line number Diff line number Diff line change
Expand Up @@ -45,12 +45,12 @@ const (
// +-------+----+-+---+
type ALUOp uint16

const aluMask OpCode = 0xfff0
const aluMask OpCode = 0x3ff0

const (
// InvalidALUOp is returned by getters when invoked
// on non ALU OpCodes
InvalidALUOp ALUOp = 0xff
InvalidALUOp ALUOp = 0xffff
// Add - addition
Add ALUOp = 0x0000
// Sub - subtraction
Expand All @@ -60,7 +60,7 @@ const (
// Div - division
Div ALUOp = 0x0030
// SDiv - signed division
SDiv ALUOp = 0x0130
SDiv ALUOp = Div + 0x0100
// Or - bitwise or
Or ALUOp = 0x0040
// And - bitwise and
Expand All @@ -74,17 +74,17 @@ const (
// Mod - modulo
Mod ALUOp = 0x0090
// SMod - signed modulo
SMod ALUOp = 0x0190
SMod ALUOp = Mod + 0x0100
// Xor - bitwise xor
Xor ALUOp = 0x00a0
// Mov - move value from one place to another
Mov ALUOp = 0x00b0
// SMov8 - move lower 8 bits, sign extended upper bits of target
SMov8 ALUOp = 0x08b0
// SMov16 - move lower 16 bits, sign extended upper bits of target
SMov16 ALUOp = 0x10b0
// SMov32 - move lower 32 bits, sign extended upper bits of target
SMov32 ALUOp = 0x20b0
// MovSX8 - move lower 8 bits, sign extended upper bits of target
MovSX8 ALUOp = Mov + 0x0100
// MovSX16 - move lower 16 bits, sign extended upper bits of target
MovSX16 ALUOp = Mov + 0x0200
// MovSX32 - move lower 32 bits, sign extended upper bits of target
MovSX32 ALUOp = Mov + 0x0300
// ArSh - arithmetic shift
ArSh ALUOp = 0x00c0
// Swap - endian conversions
Expand Down
50 changes: 25 additions & 25 deletions asm/alu_string.go
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34 changes: 22 additions & 12 deletions asm/instruction.go
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Original file line number Diff line number Diff line change
Expand Up @@ -76,13 +76,13 @@ func (ins *Instruction) Unmarshal(r io.Reader, bo binary.ByteOrder) (uint64, err
case Mov:
switch ins.Offset {
case 8:
ins.OpCode = ins.OpCode.SetALUOp(SMov8)
ins.OpCode = ins.OpCode.SetALUOp(MovSX8)
ins.Offset = 0
case 16:
ins.OpCode = ins.OpCode.SetALUOp(SMov16)
ins.OpCode = ins.OpCode.SetALUOp(MovSX16)
ins.Offset = 0
case 32:
ins.OpCode = ins.OpCode.SetALUOp(SMov32)
ins.OpCode = ins.OpCode.SetALUOp(MovSX32)
ins.Offset = 0
}
}
Expand Down Expand Up @@ -135,27 +135,37 @@ func (ins Instruction) Marshal(w io.Writer, bo binary.ByteOrder) (uint64, error)
}

if ins.OpCode.Class().IsALU() {
newOffset := int16(0)
switch ins.OpCode.ALUOp() {
case SDiv:
ins.OpCode = ins.OpCode.SetALUOp(Div)
ins.Offset = 1
newOffset = 1
case SMod:
ins.OpCode = ins.OpCode.SetALUOp(Mod)
ins.Offset = 1
case SMov8:
newOffset = 1
case MovSX8:
ins.OpCode = ins.OpCode.SetALUOp(Mov)
ins.Offset = 8
case SMov16:
newOffset = 8
case MovSX16:
ins.OpCode = ins.OpCode.SetALUOp(Mov)
ins.Offset = 16
case SMov32:
newOffset = 16
case MovSX32:
ins.OpCode = ins.OpCode.SetALUOp(Mov)
ins.Offset = 32
newOffset = 32
}
if newOffset != 0 && ins.Offset != 0 {
return 0, fmt.Errorf("extended ALU opcodes should have an .Offset of 0: %s", ins)
}
ins.Offset = newOffset
}

op, err := ins.OpCode.bpfOpCode()
if err != nil {
return 0, err
}

data := make([]byte, InstructionSize)
data[0] = byte(ins.OpCode)
data[0] = op
data[1] = byte(regs)
bo.PutUint16(data[2:4], uint16(ins.Offset))
bo.PutUint32(data[4:8], uint32(cons))
Expand Down
10 changes: 5 additions & 5 deletions asm/instruction_test.go
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Original file line number Diff line number Diff line change
Expand Up @@ -384,11 +384,11 @@ func TestISAv4(t *testing.T) {
"LdXMemSXW dst: r3 src: r6 off: 8 imm: 0",
"LdXMemSXB dst: r1 src: r4 off: 0 imm: 0",
"LdXMemSXH dst: r2 src: r5 off: 4 imm: 0",
"SMov8Reg dst: r1 src: r4",
"SMov16Reg dst: r2 src: r5",
"SMov32Reg dst: r3 src: r6",
"SMov8Reg32 dst: r1 src: r3",
"SMov16Reg32 dst: r2 src: r4",
"MovSX8Reg dst: r1 src: r4",
"MovSX16Reg dst: r2 src: r5",
"MovSX32Reg dst: r3 src: r6",
"MovSX8Reg32 dst: r1 src: r3",
"MovSX16Reg32 dst: r2 src: r4",
"Ja32 imm: 3",
"SDivReg dst: r1 src: r3",
"SModReg dst: r2 src: r4",
Expand Down
2 changes: 1 addition & 1 deletion asm/jump.go
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Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ package asm
// +----+-+---+
type JumpOp uint8

const jumpMask OpCode = aluMask
const jumpMask OpCode = 0xf0

const (
// InvalidJumpOp is returned by getters when invoked
Expand Down
19 changes: 15 additions & 4 deletions asm/opcode.go
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Original file line number Diff line number Diff line change
Expand Up @@ -72,27 +72,38 @@ func (cls Class) isJumpOrALU() bool {
// The encoding varies based on a 3-bit Class:
//
// 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
// ??? | CLS
// ??? | CLS
//
// For ALUClass and ALUCLass32:
//
// 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
// OPC |S| CLS
// OPC |S| CLS
//
// For LdClass, LdXclass, StClass and StXClass:
//
// 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
// 0 | MDE |SIZ| CLS
// 0 | MDE |SIZ| CLS
//
// For JumpClass, Jump32Class:
//
// 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
// 0 | OPC |S| CLS
// 0 | OPC |S| CLS
type OpCode uint16

// InvalidOpCode is returned by setters on OpCode
const InvalidOpCode OpCode = 0xffff

// bpfOpCode returns the actual BPF opcode.
func (op OpCode) bpfOpCode() (byte, error) {
const opCodeMask = 0xff

if !valid(op, opCodeMask) {
return 0, fmt.Errorf("invalid opcode %x", op)
}

return byte(op & opCodeMask), nil
}

// rawInstructions returns the number of BPF instructions required
// to encode this opcode.
func (op OpCode) rawInstructions() int {
Expand Down