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fix: not fully initialized wires in Edge.scala
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+ using `DontCare`
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SingularityKChen authored and sequencer committed Apr 26, 2023
1 parent 6c23100 commit 3902497
Showing 1 changed file with 10 additions and 3 deletions.
13 changes: 10 additions & 3 deletions src/main/scala/tilelink/Edges.scala
Original file line number Diff line number Diff line change
Expand Up @@ -273,17 +273,17 @@ class TLEdge(

// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, Wire(Bool()), Array(
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare), Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, Wire(Bool()), Array(
MuxLookup(a.opcode, WireDefault(Bool(), DontCare), Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, Wire(Bool()), Array(
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare), Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
Expand Down Expand Up @@ -406,6 +406,7 @@ class TLEdgeOut(

def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c :#= DontCare
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
Expand All @@ -421,6 +422,7 @@ class TLEdgeOut(

def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c :#= DontCare
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
Expand All @@ -446,6 +448,7 @@ class TLEdgeOut(
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a :#= DontCare
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
Expand All @@ -464,6 +467,7 @@ class TLEdgeOut(
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a :#= DontCare
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
Expand All @@ -482,6 +486,7 @@ class TLEdgeOut(
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a :#= DontCare
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
Expand All @@ -497,6 +502,7 @@ class TLEdgeOut(
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a :#= DontCare
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
Expand All @@ -512,6 +518,7 @@ class TLEdgeOut(
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a :#= DontCare
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
Expand Down

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