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Initial pass at Fuse Controller and Tl --> AXI replacement, pre build…
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… cleanup
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Anjana Parthasarathy committed Aug 6, 2024
1 parent cb9d70c commit c33f2f9
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15 changes: 15 additions & 0 deletions src/axi/rtl/axi_pkg.sv
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Expand Up @@ -15,6 +15,21 @@

package axi_pkg;

localparam int AXI_DW = 32;
localparam int AXI_AW = 32;
localparam int AXI_IW = 1;
localparam int AXI_BC = AXI_DW/8;
localparam int BW = $clog2(BC);

// Data that is returned upon an a TL-UL error belonging to an instruction fetch.
// Note that this data will be returned with the correct bus integrity value.
parameter logic [top_pkg::TL_DW-1:0] DataWhenInstrError = '0;
// Data that is returned upon an a TL-UL error not belonging to an instruction fetch.
// Note that this data will be returned with the correct bus integrity value.
parameter logic [top_pkg::TL_DW-1:0] DataWhenError = {top_pkg::TL_DW{1'b1}};



// AXI Burst Enum
typedef enum logic [1:0] {
AXI_BURST_FIXED = 2'b00,
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1 change: 1 addition & 0 deletions src/caliptra_prim/config/caliptra_prim.vf
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Expand Up @@ -60,3 +60,4 @@ ${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_arbiter_ppc.sv
${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_sum_tree.sv
${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_subreg_ext.sv
${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_edge_detector.sv
${CALIPTRA_ROOT}/src/caliptra_prim/rtl/caliptra_prim_blanker.sv
1 change: 1 addition & 0 deletions src/caliptra_prim/config/compile.yml
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Expand Up @@ -71,4 +71,5 @@ targets:
- $COMPILE_ROOT/rtl/caliptra_prim_sum_tree.sv
- $COMPILE_ROOT/rtl/caliptra_prim_subreg_ext.sv
- $COMPILE_ROOT/rtl/caliptra_prim_edge_detector.sv
- $COMPILE_ROOT/rtl/caliptra_prim_blanker.sv
tops: [caliptra_prim]
20 changes: 20 additions & 0 deletions src/caliptra_prim/rtl/caliptra_prim_blanker.sv
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// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

// Convenience module for wrapping prim_and2 for use in blanking.
// When en_i == 1 the input is fed through to the output.
// When en_i == 0 the output is 0.
module calipra_prim_blanker #(
parameter int Width = 1
) (
input logic [Width-1:0] in_i,
input logic en_i,
output logic [Width-1:0] out_o
);
caliptra_prim_and2 #(.Width(Width)) u_blank_and (
.in0_i(in_i),
.in1_i({Width{en_i}}),
.out_o
);
endmodule
33 changes: 33 additions & 0 deletions src/fuse_ctrl/config/config.yaml
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---
provides: [fc_ctrl]
schema_version: 2.4.0
requires:
- caliptra_prim
targets:
tb:
directories:
files:
rtl:
directories: [$COMPILE_ROOT/rtl]
files:
- $COMPILE_ROOT/rtl/axi_adapter_sram.sv
- $COMPILE_ROOT/rtl/axi_lc_gate.sv
- $COMPILE_ROOT/rtl/axi_sram_byte.sv
- $COMPILE_ROOT/rtl/caliptra_otp_ctrl_core_reg_top.sv
- $COMPILE_ROOT/rtl/caliptra_otp_ctrl_prim_reg_top.sv
- $COMPILE_ROOT/rtl/caliptra_otp_ctrl_reg_pkg.sv
- $COMPILE_ROOT/rtl/otp_ctrl_axi_pkg.sv
- $COMPILE_ROOT/rtl/otp_ctrl_dai.sv
- $COMPILE_ROOT/rtl/otp_ctrl_ecc_reg.sv
- $COMPILE_ROOT/rtl/otp_ctrl_kdi.sv
- $COMPILE_ROOT/rtl/otp_ctrl_lci.sv
- $COMPILE_ROOT/rtl/otp_ctrl_lfsr_timer.sv
- $COMPILE_ROOT/rtl/otp_ctrl_part_buf.sv
- $COMPILE_ROOT/rtl/otp_ctrl_part_pkg.sv
- $COMPILE_ROOT/rtl/otp_ctrl_part_unbuf.sv
- $COMPILE_ROOT/rtl/otp_ctrl_pkg.sv
- $COMPILE_ROOT/rtl/otp_ctrl_scrmbl.sv
- $COMPILE_ROOT/rtl/otp_ctrl.sv
- $COMPILE_ROOT/rtl/otp_ctrl.sv_orig
- $COMPILE_ROOT/rtl/otp_ctrl_token_const.sv
- $COMPILE_ROOT/rtl/otp_ctrl_top.sv
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