Add new reg fields; syntax cleanup to simulate; now passes smoke test

src/axi/rtl/axi_dma_ctrl.sv

@@ -150,8 +150,8 @@ import soc_ifc_pkg::*;
     logic [$clog2(FIFO_BC+1)-1:0] rd_credits;
     logic [AXI_LEN_BC_WIDTH-1:0] block_size_mask;
     // 1's based counters
-    logic [31-1:0] rd_bytes_requested;
-    logic [31-1:0] wr_bytes_requested;
+    logic [31:0] rd_bytes_requested;
+    logic [31:0] wr_bytes_requested;
     logic [AXI_LEN_BC_WIDTH-1:0] rd_align_req_byte_count; // byte-count in a request until nearest AXI boundary
     logic [AXI_LEN_BC_WIDTH-1:0] rd_final_req_byte_count; // byte-count in the final request, which may be smaller than a typical request
     logic [AXI_LEN_BC_WIDTH-1:0] rd_req_byte_count;       // byte-count calculated for the current read request
@@ -243,8 +243,10 @@ import soc_ifc_pkg::*;
     always_comb hwif_in.ctrl.go.hwclr    = (ctrl_fsm_ps == DMA_DONE) || ((ctrl_fsm_ps == DMA_ERROR) && hwif_out.ctrl.flush.value);
     always_comb hwif_in.ctrl.flush.hwclr = (ctrl_fsm_ps == DMA_IDLE);
 
+    always_comb hwif_in.cap.fifo_max_depth.next      = FIFO_BC/BC;
     always_comb hwif_in.status0.busy.next            = (ctrl_fsm_ps != DMA_IDLE);
     always_comb hwif_in.status0.error.next           = (ctrl_fsm_ps == DMA_ERROR);
+    always_comb hwif_in.status0.fifo_depth.next      = 12'(fifo_depth);
     always_comb hwif_in.status0.axi_dma_fsm_ps.next  = ctrl_fsm_ps;
     always_comb hwif_in.status1.bytes_remaining.next = bytes_remaining;
 
@@ -454,7 +456,7 @@ import soc_ifc_pkg::*;
         r_req_if.byte_len = rd_req_byte_count - AXI_LEN_BC_WIDTH'(BC);
         r_req_if.fixed    = hwif_out.ctrl.rd_fixed.value;
         r_req_if.lock     = 1'b0; // TODO
-        w_req_if.valid    = (ctrl_fsm_ps == DMA_WAIT_DATA) && !wr_req_hshake_bypass && (wr_bytes_requested < hwif_out.byte_count.count) && (fifo_depth >= wr_req_byte_count);
+        w_req_if.valid    = (ctrl_fsm_ps == DMA_WAIT_DATA) && !wr_req_hshake_bypass && (wr_bytes_requested < hwif_out.byte_count.count) && (fifo_depth >= wr_req_byte_count[AXI_LEN_BC_WIDTH-1:BW]);
         w_req_if.addr     = dst_addr + wr_bytes_requested;
         w_req_if.byte_len = wr_req_byte_count - AXI_LEN_BC_WIDTH'(BC);
         w_req_if.fixed    = hwif_out.ctrl.wr_fixed.value;

src/axi/rtl/axi_dma_reg.rdl

@@ -46,7 +46,8 @@ addrmap axi_dma_reg {
     reg {
         name="Caliptra AXI DMA Capabilities";
         desc="Provides information about configuration and enabled capabilities for the DMA block.";
-        field { desc="Reserved"; sw=r; } rsvd[32] = 32'h00000000;
+        field { desc="FIFO MAX DEPTH. Indicates number of available slots in the internal FIFO."; sw=r; hw=w; } fifo_max_depth[12];
+        field { desc="Reserved"; sw=r; } rsvd[20] = 20'h00000;
     } cap;
 
     reg {
@@ -107,7 +108,8 @@ addrmap axi_dma_reg {
         field { desc="Indicates if an operation has failed due to an error in decoding the command.
                       When set, this field will prevent any further operations until it is cleared by setting the ctrl.flush field.";
                 sw=r; hw=w; } error=1'b0;
-        field { desc="RESERVED."; sw=r; } rsvd0[14]=14'h0000;
+        field { desc="RESERVED."; sw=r; } rsvd0[2]=2'h0;
+        field { desc="FIFO DEPTH. Indicates number of populated slots in the internal FIFO."; sw=r; hw=w; } fifo_depth[12];
         field {
             name = "Caliptra AXI DMA FSM Present State";
             desc = "Indicates the present state of the Caliptra AXI DMA FSM.";

src/axi/rtl/axi_dma_reg.sv

@@ -2949,7 +2949,8 @@ module axi_dma_reg (
     // Assign readback values to a flattened array
     logic [45-1:0][31:0] readback_array;
     assign readback_array[0][31:0] = (decoded_reg_strb.id && !decoded_req_is_wr) ? 32'h67768068 : '0;
-    assign readback_array[1][31:0] = (decoded_reg_strb.cap && !decoded_req_is_wr) ? 32'h0 : '0;
+    assign readback_array[1][11:0] = (decoded_reg_strb.cap && !decoded_req_is_wr) ? hwif_in.cap.fifo_max_depth.next : '0;
+    assign readback_array[1][31:12] = (decoded_reg_strb.cap && !decoded_req_is_wr) ? 20'h0 : '0;
     assign readback_array[2][0:0] = (decoded_reg_strb.ctrl && !decoded_req_is_wr) ? field_storage.ctrl.go.value : '0;
     assign readback_array[2][1:1] = (decoded_reg_strb.ctrl && !decoded_req_is_wr) ? field_storage.ctrl.flush.value : '0;
     assign readback_array[2][15:2] = (decoded_reg_strb.ctrl && !decoded_req_is_wr) ? 14'h0 : '0;
@@ -2963,7 +2964,8 @@ module axi_dma_reg (
     assign readback_array[2][31:29] = (decoded_reg_strb.ctrl && !decoded_req_is_wr) ? 3'h0 : '0;
     assign readback_array[3][0:0] = (decoded_reg_strb.status0 && !decoded_req_is_wr) ? hwif_in.status0.busy.next : '0;
     assign readback_array[3][1:1] = (decoded_reg_strb.status0 && !decoded_req_is_wr) ? hwif_in.status0.error.next : '0;
-    assign readback_array[3][15:2] = (decoded_reg_strb.status0 && !decoded_req_is_wr) ? 14'h0 : '0;
+    assign readback_array[3][3:2] = (decoded_reg_strb.status0 && !decoded_req_is_wr) ? 2'h0 : '0;
+    assign readback_array[3][15:4] = (decoded_reg_strb.status0 && !decoded_req_is_wr) ? hwif_in.status0.fifo_depth.next : '0;
     assign readback_array[3][17:16] = (decoded_reg_strb.status0 && !decoded_req_is_wr) ? field_storage.status0.axi_dma_fsm_ps.value : '0;
     assign readback_array[3][31:18] = (decoded_reg_strb.status0 && !decoded_req_is_wr) ? 14'h0 : '0;
     assign readback_array[4][31:0] = (decoded_reg_strb.status1 && !decoded_req_is_wr) ? hwif_in.status1.bytes_remaining.next : '0;

src/axi/rtl/axi_dma_reg_pkg.sv

@@ -6,6 +6,14 @@ package axi_dma_reg_pkg;
     localparam AXI_DMA_REG_DATA_WIDTH = 32;
     localparam AXI_DMA_REG_MIN_ADDR_WIDTH = 12;
 
+    typedef struct packed{
+        logic [11:0] next;
+    } axi_dma_reg__cap__fifo_max_depth__in_t;
+
+    typedef struct packed{
+        axi_dma_reg__cap__fifo_max_depth__in_t fifo_max_depth;
+    } axi_dma_reg__cap__in_t;
+
     typedef struct packed{
         logic hwclr;
     } axi_dma_reg__ctrl__go__in_t;
@@ -27,13 +35,18 @@ package axi_dma_reg_pkg;
         logic next;
     } axi_dma_reg__status0__error__in_t;
 
+    typedef struct packed{
+        logic [11:0] next;
+    } axi_dma_reg__status0__fifo_depth__in_t;
+
     typedef struct packed{
         logic [1:0] next;
     } axi_dma_reg__status0__axi_dma_fsm_ps__in_t;
 
     typedef struct packed{
         axi_dma_reg__status0__busy__in_t busy;
         axi_dma_reg__status0__error__in_t error;
+        axi_dma_reg__status0__fifo_depth__in_t fifo_depth;
         axi_dma_reg__status0__axi_dma_fsm_ps__in_t axi_dma_fsm_ps;
     } axi_dma_reg__status0__in_t;
 
@@ -129,6 +142,7 @@ package axi_dma_reg_pkg;
         logic cptra_pwrgood;
         logic soc_req;
         logic dma_swwel;
+        axi_dma_reg__cap__in_t cap;
         axi_dma_reg__ctrl__in_t ctrl;
         axi_dma_reg__status0__in_t status0;
         axi_dma_reg__status1__in_t status1;

src/axi/rtl/axi_dma_reg_uvm.sv

@@ -40,8 +40,10 @@ package axi_dma_reg_uvm;
         protected uvm_reg_data_t m_data;
         protected bit            m_is_read;
 
-        axi_dma_reg__cap_bit_cg rsvd_bit_cg[32];
+        axi_dma_reg__cap_bit_cg fifo_max_depth_bit_cg[12];
+        axi_dma_reg__cap_bit_cg rsvd_bit_cg[20];
         axi_dma_reg__cap_fld_cg fld_cg;
+        rand uvm_reg_field fifo_max_depth;
         rand uvm_reg_field rsvd;
 
         function new(string name = "axi_dma_reg__cap");
@@ -54,9 +56,12 @@ package axi_dma_reg_uvm;
                                                       uvm_reg_map     map);
 
         virtual function void build();
+            this.fifo_max_depth = new("fifo_max_depth");
+            this.fifo_max_depth.configure(this, 12, 0, "RO", 1, 'h0, 0, 1, 0);
             this.rsvd = new("rsvd");
-            this.rsvd.configure(this, 32, 0, "RO", 0, 'h0, 1, 1, 0);
+            this.rsvd.configure(this, 20, 12, "RO", 0, 'h0, 1, 1, 0);
             if (has_coverage(UVM_CVR_REG_BITS)) begin
+                foreach(fifo_max_depth_bit_cg[bt]) fifo_max_depth_bit_cg[bt] = new();
                 foreach(rsvd_bit_cg[bt]) rsvd_bit_cg[bt] = new();
             end
             if (has_coverage(UVM_CVR_FIELD_VALS))
@@ -152,13 +157,15 @@ package axi_dma_reg_uvm;
 
         axi_dma_reg__status0_bit_cg busy_bit_cg[1];
         axi_dma_reg__status0_bit_cg error_bit_cg[1];
-        axi_dma_reg__status0_bit_cg rsvd0_bit_cg[14];
+        axi_dma_reg__status0_bit_cg rsvd0_bit_cg[2];
+        axi_dma_reg__status0_bit_cg fifo_depth_bit_cg[12];
         axi_dma_reg__status0_bit_cg axi_dma_fsm_ps_bit_cg[2];
         axi_dma_reg__status0_bit_cg rsvd1_bit_cg[14];
         axi_dma_reg__status0_fld_cg fld_cg;
         rand uvm_reg_field busy;
         rand uvm_reg_field error;
         rand uvm_reg_field rsvd0;
+        rand uvm_reg_field fifo_depth;
         rand uvm_reg_field axi_dma_fsm_ps;
         rand uvm_reg_field rsvd1;
 
@@ -177,7 +184,9 @@ package axi_dma_reg_uvm;
             this.error = new("error");
             this.error.configure(this, 1, 1, "RO", 1, 'h0, 1, 1, 0);
             this.rsvd0 = new("rsvd0");
-            this.rsvd0.configure(this, 14, 2, "RO", 0, 'h0, 1, 1, 0);
+            this.rsvd0.configure(this, 2, 2, "RO", 0, 'h0, 1, 1, 0);
+            this.fifo_depth = new("fifo_depth");
+            this.fifo_depth.configure(this, 12, 4, "RO", 1, 'h0, 0, 1, 0);
             this.axi_dma_fsm_ps = new("axi_dma_fsm_ps");
             this.axi_dma_fsm_ps.configure(this, 2, 16, "RO", 1, 'h0, 1, 1, 0);
             this.rsvd1 = new("rsvd1");
@@ -186,6 +195,7 @@ package axi_dma_reg_uvm;
                 foreach(busy_bit_cg[bt]) busy_bit_cg[bt] = new();
                 foreach(error_bit_cg[bt]) error_bit_cg[bt] = new();
                 foreach(rsvd0_bit_cg[bt]) rsvd0_bit_cg[bt] = new();
+                foreach(fifo_depth_bit_cg[bt]) fifo_depth_bit_cg[bt] = new();
                 foreach(axi_dma_fsm_ps_bit_cg[bt]) axi_dma_fsm_ps_bit_cg[bt] = new();
                 foreach(rsvd1_bit_cg[bt]) rsvd1_bit_cg[bt] = new();
             end

src/axi/rtl/axi_mgr_wr.sv

@@ -162,7 +162,7 @@ module axi_mgr_wr import axi_pkg::*; #(
 
     always_comb txn_final_beat = m_axi_if.wvalid && m_axi_if.wready && m_axi_if.wlast;
     always_comb begin
-        m_axi_if.wvalid = valid_i;
+        m_axi_if.wvalid = txn_active && valid_i;
         m_axi_if.wdata  = data_i;
         m_axi_if.wstrb  = '1; // TODO support this? requires significant ctrl updates
         m_axi_if.wlast = ~|txn_down_cnt;

src/axi/rtl/caliptra_axi_sram.sv

@@ -86,7 +86,7 @@ caliptra_sram #(
 
     .cs_i    (dv   ),
     .we_i    (write),
-    .addr_i  (addr ),
+    .addr_i  (addr[AW-1:BW]),
     .wdata_i (wdata),
     .rdata_o (rdata)
 );