Exclusive access support OFF by default

chipsalliance · Jul 25, 2024 · a9a17f7 · a9a17f7
1 parent f5b883f
commit a9a17f7
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/axi/rtl/axi_sub_rd.sv b/src/axi/rtl/axi_sub_rd.sv
@@ -34,7 +34,7 @@ module axi_sub_rd import axi_pkg::*; #(
     parameter IW = 1,          // ID Width
               ID_NUM = 1 << IW, // Don't override
 
-    parameter EX_EN = 1,   // Enable exclusive access tracking w/ AxLOCK
+    parameter EX_EN = 0,   // Enable exclusive access tracking w/ AxLOCK
     parameter C_LAT = 0    // Component latency in clock cycles from (dv&&!hld) -> rdata
                            // Must be const per component
                            // For registers, typically 0