Add component inf 'write' signal

chipsalliance · May 31, 2024 · 65dd299 · 65dd299
1 parent 5f5b0ef
commit 65dd299
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Showing 2 changed files with 4 additions and 0 deletions.
diff --git a/src/axi/rtl/axi_sub.sv b/src/axi/rtl/axi_sub.sv
@@ -52,6 +52,7 @@ module axi_sub import axi_pkg::*; #(
     //COMPONENT INF
     output logic          dv,
     output logic [AW-1:0] addr, // Byte address
+    output logic          write,
     output logic [UW-1:0] user,
     output logic [IW-1:0] id,
     output logic [DW-1:0] wdata, // Requires: Component dwidth == AXI dwidth
@@ -191,6 +192,7 @@ module axi_sub import axi_pkg::*; #(
         //COMPONENT INF
         .dv     (dv     ),
         .addr   (addr   ),
+        .write  (write  ),
         .user   (user   ),
         .id     (id     ),
         .wdata  (wdata  ),

diff --git a/src/axi/rtl/axi_sub_arb.sv b/src/axi/rtl/axi_sub_arb.sv
@@ -65,6 +65,7 @@ module axi_sub_arb import axi_pkg::*; #(
     //COMPONENT INF
     output logic          dv,
     output logic [AW-1:0] addr, // Byte address
+    output logic          write,
     output logic [UW-1:0] user,
     output logic [IW-1:0] id,
     output logic [DW-1:0] wdata, // Requires: Component dwidth == AXI dwidth
@@ -118,6 +119,7 @@ module axi_sub_arb import axi_pkg::*; #(
     always_comb begin
         dv      = r_dv || w_dv;
         addr    = r_win ? r_addr : w_addr;
+        write   = r_win ?      0 :      1;
         user    = r_win ? r_user : w_user;
         id      = r_win ? r_id   : w_id  ;
         last    = r_win ? r_last : w_last;