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TB updates to support all prev. functionality; smoke_test_dma passes;…
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… add AXI assertions
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@calebofearth
calebofearth committed Jul 25, 2024
1 parent b3e2b6c commit 2f8d8c0
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Showing 23 changed files with 1,080 additions and 958 deletions.
35 changes: 22 additions & 13 deletions src/axi/rtl/axi_dma_ctrl.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -99,7 +99,7 @@ import soc_ifc_pkg::*;
axi_dma_reg_pkg::axi_dma_reg__in_t hwif_in;
axi_dma_reg_pkg::axi_dma_reg__out_t hwif_out;

enum logic [2:0] {
enum logic [1:0] {
DMA_IDLE,
DMA_WAIT_DATA,
DMA_DONE,
Expand Down Expand Up @@ -237,6 +237,9 @@ import soc_ifc_pkg::*;
ctrl_fsm_ns = DMA_IDLE;
end
end
default: begin
ctrl_fsm_ns = ctrl_fsm_ps;
end
endcase
end

Expand Down Expand Up @@ -337,7 +340,7 @@ import soc_ifc_pkg::*;
((hwif_out.ctrl.rd_route.value == axi_dma_reg__ctrl__rd_route__rd_route_e__MBOX) ||
(hwif_out.ctrl.wr_route.value == axi_dma_reg__ctrl__wr_route__wr_route_e__MBOX)));
// power of 2 and word-aligned
cmd_inv_block_size = |(hwif_out.block_size.size.value & hwif_out.block_size.size.value) ||
cmd_inv_block_size = |(hwif_out.block_size.size.value & (hwif_out.block_size.size.value-1)) ||
|hwif_out.block_size.size.value[BW-1:0];
cmd_inv_rd_fixed = hwif_out.ctrl.rd_fixed.value && hwif_out.ctrl.rd_route.value == axi_dma_reg__ctrl__rd_route__rd_route_e__DISABLE;
cmd_inv_wr_fixed = hwif_out.ctrl.wr_fixed.value && hwif_out.ctrl.wr_route.value == axi_dma_reg__ctrl__wr_route__wr_route_e__DISABLE;
Expand Down Expand Up @@ -413,12 +416,12 @@ import soc_ifc_pkg::*;
else if (hwif_out.block_size.size.value == 0) begin
rd_req_stall <= 1'b0;
end
else if (rd_req_hshake) begin
rd_req_stall <= 1'b1;
end
else if (recovery_data_avail) begin
rd_req_stall <= 1'b0;
end
else if (rd_req_hshake || hwif_out.ctrl.go.value) begin
rd_req_stall <= 1'b1;
end
end

always_ff @(posedge clk or negedge rst_n) begin
Expand All @@ -440,11 +443,13 @@ import soc_ifc_pkg::*;

always_comb block_size_mask = hwif_out.block_size.size.value - 1;
always_comb begin
rd_align_req_byte_count = (MAX_BLOCK_SIZE - r_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) & block_size_mask;
rd_align_req_byte_count = ~|hwif_out.block_size.size.value || (MAX_BLOCK_SIZE < hwif_out.block_size.size.value) ? (MAX_BLOCK_SIZE - r_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) :
hwif_out.block_size.size.value - (r_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0] & block_size_mask);
rd_final_req_byte_count = hwif_out.byte_count.count.value - rd_bytes_requested;
rd_req_byte_count = rd_final_req_byte_count < rd_align_req_byte_count ? rd_final_req_byte_count :
rd_align_req_byte_count;
wr_align_req_byte_count = (MAX_BLOCK_SIZE - w_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) & block_size_mask;
wr_align_req_byte_count = ~|hwif_out.block_size.size.value || (MAX_BLOCK_SIZE < hwif_out.block_size.size.value) ? (MAX_BLOCK_SIZE - w_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0]) :
hwif_out.block_size.size.value - (w_req_if.addr[$clog2(MAX_BLOCK_SIZE)-1:0] & block_size_mask);
wr_final_req_byte_count = hwif_out.byte_count.count.value - wr_bytes_requested;
wr_req_byte_count = wr_final_req_byte_count < wr_align_req_byte_count ? wr_final_req_byte_count :
wr_align_req_byte_count;
Expand Down Expand Up @@ -650,11 +655,15 @@ import soc_ifc_pkg::*;
end
end

`ifdef VERILATOR
FIXME_ASSERT_INIT(DW == 32)
FIXME_ASSERT(rd_credits <= FIFO_BC)
FIXME_ASSERT(!((rd_credits < BC) && rd_req_hshake))
FIXME_ASSERT(!((ctrl_fsm_ps == DMA_DONE) && (rd_credits != FIFO_BC)))
`endif
// Requests must have valid length
`CALIPTRA_ASSERT(AXI_DMA_VLD_RD_REQ_LEN, rd_req_hshake |-> r_req_if.byte_len < MAX_BLOCK_SIZE, clk, !rst_n)
`CALIPTRA_ASSERT(AXI_DMA_VLD_WR_REQ_LEN, wr_req_hshake |-> w_req_if.byte_len < MAX_BLOCK_SIZE, clk, !rst_n)
// Requests must not cross AXI boundary (4KiB)
`CALIPTRA_ASSERT(AXI_DMA_VLD_RD_REQ_BND, rd_req_hshake |-> r_req_if.addr[AW-1:AXI_LEN_BC_WIDTH] == ((r_req_if.addr + r_req_if.byte_len) >> AXI_LEN_BC_WIDTH), clk, !rst_n)
`CALIPTRA_ASSERT(AXI_DMA_VLD_WR_REQ_BND, wr_req_hshake |-> w_req_if.addr[AW-1:AXI_LEN_BC_WIDTH] == ((w_req_if.addr + w_req_if.byte_len) >> AXI_LEN_BC_WIDTH), clk, !rst_n)
`CALIPTRA_ASSERT_INIT(AXI_DMA_DW_32, DW == 32)
`CALIPTRA_ASSERT(AXI_DMA_LIM_RD_CRED, rd_credits <= FIFO_BC, clk, !rst_n)
`CALIPTRA_ASSERT(AXI_DMA_MIN_RD_CRED, !((rd_credits < BC) && rd_req_hshake), clk, !rst_n)
`CALIPTRA_ASSERT(AXI_DMA_RST_RD_CRED, (ctrl_fsm_ps == DMA_DONE) |-> (rd_credits == FIFO_BC), clk, !rst_n)

endmodule
2 changes: 1 addition & 1 deletion src/axi/rtl/axi_dma_reg.rdl
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Original file line number Diff line number Diff line change
Expand Up @@ -167,7 +167,7 @@ addrmap axi_dma_reg {
// Byte Count
reg {
name="Caliptra AXI DMA Byte Count";
desc="Contains total number of bytes to be transferred by current operation.";
desc="Contains total number of bytes to be transferred by current operation. Must be a multiple of the AXI Data Width. (Narrow/unaligned transfers are not supported)";
field { desc="Byte Count"; sw=rw; swwel=dma_swwel; hw=r; } count[32]=32'h00000000;
} byte_count;

Expand Down
10 changes: 4 additions & 6 deletions src/axi/rtl/axi_mgr_rd.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -179,12 +179,10 @@ module axi_mgr_rd import axi_pkg::*; #(
// --------------------------------------- //
// Assertions //
// --------------------------------------- //
`ifdef VERILATOR
`FIXME_ASSERT(req.valid && addr + len <= 4096)
`FIXME_ASSERT(req_if.byte_len[11:10] == 2'b00)
`FIXME_ASSERT(req_if.rvalid && txn_active)
`FIXME_ASSERT_NEVER(fixme_valid_and_ready && ready_i, "Received data with no space in FIFO! Is the FSM credit calculation wrong?")
`endif
`CALIPTRA_ASSERT(AXI_MGR_REQ_BND, req_if.valid |-> ((req_if.addr[11:0] + req_if.byte_len) <= 4096), clk, !rst_n)
`CALIPTRA_ASSERT(AXI_MGR_LEGAL_LEN, req_if.valid |-> (req_if.byte_len[AXI_LEN_BC_WIDTH-1:BW]) < AXI_LEN_MAX_VALUE, clk, !rst_n)
`CALIPTRA_ASSERT(AXI_MGR_DATA_WHILE_ACTIVE, valid_o |-> txn_active, clk, !rst_n)
`CALIPTRA_ASSERT_NEVER(AXI_MGR_OFLOW, m_axi_if.rready && !ready_i, clk, !rst_n)


endmodule
9 changes: 4 additions & 5 deletions src/axi/rtl/axi_mgr_wr.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -181,10 +181,9 @@ module axi_mgr_wr import axi_pkg::*; #(
// --------------------------------------- //
// Assertions //
// --------------------------------------- //
`ifdef VERILATOR
`FIXME_ASSERT(req.valid && addr + len <= 4096)
`FIXME_ASSERT(req_if.byte_len[11:10] == 2'b00)
`FIXME_ASSERT(req_if.rvalid && txn_active)
`endif
`CALIPTRA_ASSERT(AXI_MGR_REQ_BND, req_if.valid |-> ((req_if.addr[11:0] + req_if.byte_len) <= 4096), clk, !rst_n)
`CALIPTRA_ASSERT(AXI_MGR_LEGAL_LEN, req_if.valid |-> (req_if.byte_len[AXI_LEN_BC_WIDTH-1:BW]) < AXI_LEN_MAX_VALUE, clk, !rst_n)
`CALIPTRA_ASSERT(AXI_MGR_DATA_WHILE_ACTIVE, ready_o |-> txn_active, clk, !rst_n)
`CALIPTRA_ASSERT_NEVER(AXI_MGR_UFLOW, m_axi_if.wvalid && !valid_i, clk, !rst_n)

endmodule
43 changes: 21 additions & 22 deletions src/axi/rtl/axi_sub_rd.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -103,8 +103,8 @@ module axi_sub_rd import axi_pkg::*; #(
logic [AW-1:0] txn_addr_nxt;
logic [ 7:0] txn_cnt; // Internal down-counter to track txn progress
logic txn_active;
logic [C_LAT:0] txn_rvalid;
xfer_ctx_t [C_LAT:0] txn_xfer_ctx;
logic txn_rvalid [C_LAT+1];
xfer_ctx_t txn_xfer_ctx [C_LAT+1];
logic txn_final_beat;

// Data pipeline signals (skid buffer)
Expand Down Expand Up @@ -168,9 +168,9 @@ module axi_sub_rd import axi_pkg::*; #(

// Only make the request to component if we have space in the pipeline to
// store the result (under worst-case AXI backpressure)
// To check this, look at the 'ready' output from the FINAL stage of the
// To check this, look at the 'ready' output from all stages of the
// skidbuffer pipeline
always_comb dv = txn_active && dp_rready[C_LAT];
always_comb dv = txn_active && &dp_rready;
always_comb txn_rvalid[0] = dv && !hld;

// Asserts on the final beat of the COMPONENT INF which means it lags the
Expand Down Expand Up @@ -212,25 +212,23 @@ module axi_sub_rd import axi_pkg::*; #(
// Shift Register to track requests made to component
generate
if (C_LAT > 0) begin: TXN_SR
always_ff@(posedge clk or negedge rst_n) begin
if (!rst_n) begin
txn_rvalid[C_LAT:1] <= C_LAT'(0);
end
else begin
txn_rvalid[C_LAT:1] <= txn_rvalid[C_LAT-1:0];
end
end

// Context is maintained alongside request while waiting for
// component response to arrive
if (C_LAT > 1) begin
for (cp = 1; cp <= C_LAT; cp++) begin: CTX_PIPELINE
// No reset needed on data path -- txn_rvalid (control path) is reset
always_ff@(posedge clk) begin
txn_xfer_ctx[cp] <= txn_xfer_ctx[cp-1];
for (cp = 1; cp <= C_LAT; cp++) begin: CTX_PIPELINE
always_ff@(posedge clk or negedge rst_n) begin
if (!rst_n) begin
txn_rvalid[cp] <= 1'b0;
end
end: CTX_PIPELINE
end
else begin
txn_rvalid[cp] <= txn_rvalid[cp-1];
end
end

// No reset needed on data path -- txn_rvalid (control path) is reset
always_ff@(posedge clk) begin
txn_xfer_ctx[cp] <= txn_xfer_ctx[cp-1];
end
end: CTX_PIPELINE

end: TXN_SR
endgenerate
Expand Down Expand Up @@ -395,8 +393,9 @@ module axi_sub_rd import axi_pkg::*; #(
generate
if (C_LAT > 0) begin
for (sva_ii = 0; sva_ii < C_LAT; sva_ii++) begin
// Last stage should be first to fill and last to go empty
`CALIPTRA_ASSERT_NEVER(ERR_RD_SKD_BUF, dp_rready[sva_ii+1] && !dp_rready[sva_ii], clk, !rst_n)
// Last stage should be first to fill and first to go empty
`CALIPTRA_ASSERT_NEVER(ERR_RD_SKD_BUF_FILL, $fell(dp_rready[sva_ii+1]) && !dp_rready[sva_ii], clk, !rst_n)
`CALIPTRA_ASSERT_NEVER(ERR_RD_SKD_BUF_DRAIN, $rose(dp_rready[sva_ii+1]) && dp_rready[sva_ii], clk, !rst_n)
end
end
endgenerate
Expand Down
8 changes: 7 additions & 1 deletion src/integration/rtl/caliptra_reg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -5368,6 +5368,10 @@
#define AXI_DMA_REG_ID (0x0)
#define CLP_AXI_DMA_REG_CAP (0x30022004)
#define AXI_DMA_REG_CAP (0x4)
#define AXI_DMA_REG_CAP_FIFO_MAX_DEPTH_LOW (0)
#define AXI_DMA_REG_CAP_FIFO_MAX_DEPTH_MASK (0xfff)
#define AXI_DMA_REG_CAP_RSVD_LOW (12)
#define AXI_DMA_REG_CAP_RSVD_MASK (0xfffff000)
#define CLP_AXI_DMA_REG_CTRL (0x30022008)
#define AXI_DMA_REG_CTRL (0x8)
#define AXI_DMA_REG_CTRL_GO_LOW (0)
Expand Down Expand Up @@ -5399,7 +5403,9 @@
#define AXI_DMA_REG_STATUS0_ERROR_LOW (1)
#define AXI_DMA_REG_STATUS0_ERROR_MASK (0x2)
#define AXI_DMA_REG_STATUS0_RSVD0_LOW (2)
#define AXI_DMA_REG_STATUS0_RSVD0_MASK (0xfffc)
#define AXI_DMA_REG_STATUS0_RSVD0_MASK (0xc)
#define AXI_DMA_REG_STATUS0_FIFO_DEPTH_LOW (4)
#define AXI_DMA_REG_STATUS0_FIFO_DEPTH_MASK (0xfff0)
#define AXI_DMA_REG_STATUS0_AXI_DMA_FSM_PS_LOW (16)
#define AXI_DMA_REG_STATUS0_AXI_DMA_FSM_PS_MASK (0x30000)
#define AXI_DMA_REG_STATUS0_RSVD1_LOW (18)
Expand Down
8 changes: 7 additions & 1 deletion src/integration/rtl/caliptra_reg_defines.svh
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Original file line number Diff line number Diff line change
Expand Up @@ -5368,6 +5368,10 @@
`define AXI_DMA_REG_ID (32'h0)
`define CLP_AXI_DMA_REG_CAP (32'h30022004)
`define AXI_DMA_REG_CAP (32'h4)
`define AXI_DMA_REG_CAP_FIFO_MAX_DEPTH_LOW (0)
`define AXI_DMA_REG_CAP_FIFO_MAX_DEPTH_MASK (32'hfff)
`define AXI_DMA_REG_CAP_RSVD_LOW (12)
`define AXI_DMA_REG_CAP_RSVD_MASK (32'hfffff000)
`define CLP_AXI_DMA_REG_CTRL (32'h30022008)
`define AXI_DMA_REG_CTRL (32'h8)
`define AXI_DMA_REG_CTRL_GO_LOW (0)
Expand Down Expand Up @@ -5399,7 +5403,9 @@
`define AXI_DMA_REG_STATUS0_ERROR_LOW (1)
`define AXI_DMA_REG_STATUS0_ERROR_MASK (32'h2)
`define AXI_DMA_REG_STATUS0_RSVD0_LOW (2)
`define AXI_DMA_REG_STATUS0_RSVD0_MASK (32'hfffc)
`define AXI_DMA_REG_STATUS0_RSVD0_MASK (32'hc)
`define AXI_DMA_REG_STATUS0_FIFO_DEPTH_LOW (4)
`define AXI_DMA_REG_STATUS0_FIFO_DEPTH_MASK (32'hfff0)
`define AXI_DMA_REG_STATUS0_AXI_DMA_FSM_PS_LOW (16)
`define AXI_DMA_REG_STATUS0_AXI_DMA_FSM_PS_MASK (32'h30000)
`define AXI_DMA_REG_STATUS0_RSVD1_LOW (18)
Expand Down
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