allow different module names for verilog export

[mattvenn]

currently the module is always exported with name top, which tends to interfere with the traditional name of the top level module in any existing project.

would be good to have a box to type the name of the desired module.

[chipmuenk]

You're right, "filter" or a user supplied name would be better. Nice that someone is using that feature :-)
Currently, Verilog export is more a proof of concept (not sure if it makes sense to generate a netlist for a FIR filter when most FPGA tools have optimized FIR Cores that just need the coefficients). At the moment, we are working on a (n)Migen implementation for IIR filters, I'll add a text entry for the module name then.

[mattvenn]

Hi,
yes I've been experimenting with it recently. I'm using it with the open source toolchain, and we don't have FIR implementations (as far as I know), so this tool is actually really interesting for that.
Thanks,
Matt

[chipmuenk]

In the master branch, the top level module name now is derived from the Verilog file name (lower cased and sanitized i.e. removing all non-alphanumeric characters. Please check whether this works for you, it will also be part of v0.4.0 that will be released in the next 1 ... 2 weeks.

[mattvenn]

nice!

…

On Sun, 27 Sep 2020 at 19:42, Christian Münker ***@***.***> wrote: In the master branch, the top level module name now is derived from the Verilog file name (lower cased and sanitized i.e. removing all non-alphanumeric characters. Please check whether this works for you, it will also be part of v0.4.0 that will be released in the next 1 ... 2 weeks. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub <#176 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AAE223GFPISQRMR6CWUSRCLSH52QRANCNFSM4N3Q7UIQ> .

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