aarch64: Add support for the extr instruction
#10229
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This is pattern-matched from `bor` patterns of a specific shape. I found this when doing some benchmarking of Wasmtime on aarch64 and I saw LLVM generating this pattern but Wasmtime didn't. I didn't perform any benchmarking between wasmtime/native though, so I'm just relying on this reducing the number of instructions to probably be a wee bit faster.
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alexcrichton
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This commit is similar to bytecodealliance#10229 except that it uses the x64 `shld` instruction. This instruction was not previously supported by Cranelift so I opted to add support via the new `cranelift-assembler-x64` crate instead of trying to fit it into the existing `emit.rs`/`MInst` infrastructure. This was a good learning experience for myself and was also fun to do!
alexcrichton
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Feb 14, 2025
This commit is similar to bytecodealliance#10229 except that it uses the x64 `shld` instruction. This instruction was not previously supported by Cranelift so I opted to add support via the new `cranelift-assembler-x64` crate instead of trying to fit it into the existing `emit.rs`/`MInst` infrastructure. This was a good learning experience for myself and was also fun to do!
github-merge-queue bot
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Feb 14, 2025
This commit is similar to #10229 except that it uses the x64 `shld` instruction. This instruction was not previously supported by Cranelift so I opted to add support via the new `cranelift-assembler-x64` crate instead of trying to fit it into the existing `emit.rs`/`MInst` infrastructure. This was a good learning experience for myself and was also fun to do!
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This is pattern-matched from
borpatterns of a specific shape. I found this when doing some benchmarking of Wasmtime on aarch64 and I saw LLVM generating this pattern but Wasmtime didn't. I didn't perform any benchmarking between wasmtime/native though, so I'm just relying on this reducing the number of instructions to probably be a wee bit faster.