Reduce ILA size

bittide · Feb 22, 2025 · 5ff5ed4 · 5ff5ed4
1 parent b62aec5
commit 5ff5ed4
Showing 1 changed file with 17 additions and 59 deletions.
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/FullMeshSwCc.hs b/bittide-instances/src/Bittide/Instances/Hitl/FullMeshSwCc.hs
@@ -317,21 +317,21 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
     , ugnD5
     , ugnD6
     ) = vecToTuple freeUgnDatas
-  (ugn0, fill0, ugnStable0, fillStats0) = unbundle ugnD0
-  (ugn1, fill1, ugnStable1, fillStats1) = unbundle ugnD1
-  (ugn2, fill2, ugnStable2, fillStats2) = unbundle ugnD2
-  (ugn3, fill3, ugnStable3, fillStats3) = unbundle ugnD3
-  (ugn4, fill4, ugnStable4, fillStats4) = unbundle ugnD4
-  (ugn5, fill5, ugnStable5, fillStats5) = unbundle ugnD5
-  (ugn6, fill6, ugnStable6, fillStats6) = unbundle ugnD6
-
-  FillStats fillMin0 fillMax0 = unbundle fillStats0
-  FillStats fillMin1 fillMax1 = unbundle fillStats1
-  FillStats fillMin2 fillMax2 = unbundle fillStats2
-  FillStats fillMin3 fillMax3 = unbundle fillStats3
-  FillStats fillMin4 fillMax4 = unbundle fillStats4
-  FillStats fillMin5 fillMax5 = unbundle fillStats5
-  FillStats fillMin6 fillMax6 = unbundle fillStats6
+  (ugn0, _fill0, ugnStable0, fillStats0) = unbundle ugnD0
+  (ugn1, _fill1, ugnStable1, fillStats1) = unbundle ugnD1
+  (ugn2, _fill2, ugnStable2, fillStats2) = unbundle ugnD2
+  (ugn3, _fill3, ugnStable3, fillStats3) = unbundle ugnD3
+  (ugn4, _fill4, ugnStable4, fillStats4) = unbundle ugnD4
+  (ugn5, _fill5, ugnStable5, fillStats5) = unbundle ugnD5
+  (ugn6, _fill6, ugnStable6, fillStats6) = unbundle ugnD6
+
+  FillStats _fillMin0 _fillMax0 = unbundle fillStats0
+  FillStats _fillMin1 _fillMax1 = unbundle fillStats1
+  FillStats _fillMin2 _fillMax2 = unbundle fillStats2
+  FillStats _fillMin3 _fillMax3 = unbundle fillStats3
+  FillStats _fillMin4 _fillMax4 = unbundle fillStats4
+  FillStats _fillMin5 _fillMax5 = unbundle fillStats5
+  FillStats _fillMin6 _fillMax6 = unbundle fillStats6
 
   allReady =
     trueFor (SNat @(Milliseconds 500)) sysClk syncRst (and <$> bundle transceivers.linkReadys)
@@ -409,27 +409,6 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
             :> "probe_rx_ugn4"
             :> "probe_rx_ugn5"
             :> "probe_rx_ugn6"
-            :> "probe_fill0"
-            :> "probe_fill2"
-            :> "probe_fill1"
-            :> "probe_fill3"
-            :> "probe_fill4"
-            :> "probe_fill5"
-            :> "probe_fill6"
-            :> "probe_fillMin0"
-            :> "probe_fillMin2"
-            :> "probe_fillMin1"
-            :> "probe_fillMin3"
-            :> "probe_fillMin4"
-            :> "probe_fillMin5"
-            :> "probe_fillMin6"
-            :> "probe_fillMax0"
-            :> "probe_fillMax2"
-            :> "probe_fillMax1"
-            :> "probe_fillMax3"
-            :> "probe_fillMax4"
-            :> "probe_fillMax5"
-            :> "probe_fillMax6"
             :> "stability0"
             :> "stability2"
             :> "stability1"
@@ -450,11 +429,11 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
             :> "fifoOverflows"
             :> Nil
         )
-          { depth = D16384
+          { depth = D4096
           }
         sysClk
         -- Trigger as soon as we come out of reset
-        (unsafeToActiveLow syncRst)
+        allStable0
         capture
         -- Debug probes
         milliseconds1
@@ -478,27 +457,6 @@ fullMeshHwTest refClk sysClk IlaControl{syncRst = rst, ..} rxNs rxPs miso =
         (snd <$> ugn4)
         (snd <$> ugn5)
         (snd <$> ugn6)
-        fill0
-        fill1
-        fill2
-        fill3
-        fill4
-        fill5
-        fill6
-        fillMin0
-        fillMin1
-        fillMin2
-        fillMin3
-        fillMin4
-        fillMin5
-        fillMin6
-        fillMax0
-        fillMax1
-        fillMax2
-        fillMax3
-        fillMax4
-        fillMax5
-        fillMax6
         stability0
         stability1
         stability2