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Fix reconvergence issue in synchronizer (#150)
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bensampson5 authored Feb 7, 2022
1 parent 6e8d336 commit 989a51a
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Showing 2 changed files with 7 additions and 9 deletions.
13 changes: 6 additions & 7 deletions libsv/synchronizers/synchronizer.sv
Original file line number Diff line number Diff line change
Expand Up @@ -2,16 +2,15 @@
`define LIBSV_SYNCHRONIZERS_SYNCHRONIZER

module synchronizer #(
parameter int DATA_WIDTH /* verilator public_flat_rd */ = 1,
parameter int FF_STAGES /* verilator public_flat_rd */ = 2
parameter int FF_STAGES /* verilator public_flat_rd */ = 2
) (
input logic i_clock,
input logic i_aresetn,
input logic [DATA_WIDTH-1:0] i_data,
output logic [DATA_WIDTH-1:0] o_data
input logic i_clock,
input logic i_aresetn,
input logic i_data,
output logic o_data
);

logic [FF_STAGES-1:0][DATA_WIDTH-1:0] sync_mem;
logic [FF_STAGES-1:0] sync_mem;

always_ff @(posedge i_clock, negedge i_aresetn) begin
if (!i_aresetn) begin
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3 changes: 1 addition & 2 deletions tests/synchronizers/test_synchronizer.py
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,6 @@ def test_synchonrizer(pytestconfig):
async def cocotb_test_synchonrizer(dut):
"""Synchronizer test"""

data_width = int(dut.DATA_WIDTH)
ff_stages = int(dut.FF_STAGES)

cocotb.fork(Clock(dut.i_clock, 2).start())
Expand All @@ -22,7 +21,7 @@ async def cocotb_test_synchonrizer(dut):
await FallingEdge(dut.i_clock)
dut.i_aresetn.value = 1

sync_value = 1 % (2 ** data_width)
sync_value = 1
dut.i_data.value = sync_value
for _ in range(ff_stages):
assert dut.o_data.value != sync_value
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