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REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
BEAGLEBONE BLACK ADDITIONAL TERMS
BeagleBoard.org, Circuitco, LLC, and BeagleBoard.org (Supplier) provide the enclosed BeagleBone under the following conditions:
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies Supplier from all claims arising from the handling or use of the goods.
Should the BeagleBone not meet the specifications indicated in the System Reference Manual, the BeagleBone may be returned within 90 days from the date of delivery to the distributor of purchase for a full refund. THE FOREGOING LIMITED WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
Please read the System Reference Manual and, specifically, the Warnings and Restrictions notice in the Systems Reference Manual prior to handling the product. This notice contains important safety information about temperatures and voltages.
No license is granted under any patent right or other intellectual property right of Supplier covering or relating to any machine, process, or combination in which such Supplier products or services might be or are used. The Supplier currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive. The Supplier assume no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein.
UNITED STATES FCC AND CANADA IC REGULATORY COMPLIANCE INFORMATION
The BeagleBone is annotated to comply with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment.
This Class A or B digital apparatus complies with Canadian ICES-003. Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment. Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada. Les changements ou les modifications pas expressément approuvés par la partie responsible de la conformité ont pu vider l’autorité de l’utilisateur pour actionner l’équipement.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
accordance with the terms of the agreement. This obligation shall apply whether Claims arise under law of tort or contract or any other legal theory, and even if the BeagleBone fails to perform as described or expected.
*Safety-Critical or Life-Critical Applications*. If you intend to evaluate the components for possible use in safety critical applications (such as life support) where a failure of the Supplier’s product would reasonably be expected to cause severe personal injury or death, such as devices which are classified as FDA Class III or similar classification, then you must specifically notify Suppliers of such intent and enter into a separate Assurance and Indemnity Agreement.
Mailing Address:
BeagleBoard.org
1380 Presidential Dr. #100
Richardson, TX 75081
U.S.A.
WARRANTY: The BeagleBone Black Assembly as purchased is warranted against defects in materials and workmanship for a period of 90 days from purchase. This warranty does not cover any problems occurring as a result of improper use, modifications, exposure to water, excessive voltages, abuse, or accidents. All boards will be returned via standard mail if an issue is found. If no issue is found or express return is needed, the customer will pay all shipping costs.
For up to date SW images and technical information refer to http://circuitco.com/support/index.php?title=BeagleBoneBlack
All support for this board is provided via community support at www.beagleboard.org/discuss
To return a defective board for repair, please request an RMA at http://beagleboard.org/support/rma
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
This document is the System Reference Manual for the BeagleBone Black and covers its use and design. The board will primarily be referred to in the remainder of this document simply as the board, although it may also be referred to as the BeagleBone Black as a reminder. There are also references to the original BeagleBone as well, and will be referenced as simply BeagleBone.
This design is subject to change without notice as we will work to keep improving the design as the product matures based on feedback and experience. Software updates will be frequent and will be independent of the hardware revisions and as such not result in a change in the revision number.
Make sure you check the support Wiki frequently for the most up to date information.
This section describes the change history of this document and board. Document changes are not always a result of a board change. A board change will always result in a document change.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
Figure 19 below is the high level block diagram of the BeagleBone Black.
The revision B board has moved to the Sitara AM3358BZCZ100 device.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
-
eMMC Boot…This is the default boot mode and will allow for the fastest boot time and will enable the board to boot out of the box using the pre-flashed OS image without having to purchase an microSD card or an microSD card writer.
-
SD Boot…This mode will boot from the microSD slot. This mode can be used to override what is on the eMMC device and can be used to program the eMMC when used in the manufacturing process or for field updates.
-
Serial Boot…This mode will use the serial port to allow downloading of the software direct. A separate USB to serial cable is required to use this port.
-
USB Boot…This mode supports booting over the USB port.
Software to support USB and serial boot modes is not provided by beagleboard.org.
Please contact TI for support of this feature.
A switch is provided to allow switching between the modes.
-
Holding the boot switch down during a removal and reapplication of power without a microSD card inserted will force the boot source to be the USB port and if nothing is detected on the USB client port, it will go to the serial port for download.
-
Without holding the switch, the board will boot try to boot from the eMMC. If it is empty, then it will try booting from the microSD slot, followed by the serial port, and then the USB port.
-
If you hold the boot switch down during the removal and reapplication of power to the board, and you have a microSD card inserted with a bootable image, the board will boot from the microSD card.
NOTE: Pressing the RESET button on the board will NOT result in a change of the boot mode. You MUST remove power and reapply power to change the boot mode. The boot pins are sampled during power on reset from the PMIC to the processor. The reset button on the board is a warm reset only and will not force a boot mode change.
The TPS65217C power management device is used along with a separate LDO to provide power to the system. The TPS65217C version provides for the proper voltages required for the DDR3L. This is the same device as used on the original BeagleBone with the exception of the power rail configuration settings which will be changed in the internal EEPROM to the TPS65217C to support the new voltages.
DDR3L requires 1.5V instead of 1.8V on the DDR2 as is the case on the original BeagleBone. The 1.8V regulator setting has been changed to 1.5V for the DDR3L. The
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
plugged into the board or you have a power hungry device or hub plugged into the host port, then more current may needed from the DC supply.
Power routed to the board via the expansion header could be provided from power derived on a cape. The DC supply should be well regulated and 5V +/-.25V.
When pressed and released, causes a reset of the board. The reset button used on the BeagleBone Black is a little larger than the one used on the original BeagleBone. It has also been moved out to the edge of the board so that it is more accessible.
A power button is provided near the reset button close to the Ethernet connector. This button takes advantage of the input to the PMIC for power down features. While a lot of capes have a button, it was decided to add this feature to the board to ensure everyone had access to some new features. These features include:
-
Interrupt is sent to the processor to facilitate an orderly shutdown to save files and to un-mount drives.
-
Provides ability to let processor put board into a sleep mode to save power.
-
Can alert processor to wake up from sleep mode and restore state before sleep was entered.
If you hold the button down longer than 8 seconds, the board will power off if you release the button when the power LED turns off. If you continue to hold it, the board will power back up completing a power cycle.
We recommend that you use this method to power down the board. It will also help prevent contamination of the SD card or the eMMC.
If you do not remove the power jack, you can press the button again and the board will power up.
There are a total of five blue LEDs on the board.
-
One blue power LED indicates that power is applied and the power management IC is up. If this LED flashes when applying power, it means that an excess current flow was detected and the PMIC has shut down.
-
Four blue LEDs that can be controlled via the SW by setting GPIO pins.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
-
GPMC bus may NOT be available due to the use of those signals by the eMMC. If the eMMC is used for booting only and the file system is on the microSD card, then these signals could be used.
-
Another option is to use the microSD or serial boot modes and not use the eMMC.
-
The power expansion header is not on the BeagleBone Black so those functions are not supported.
For more information on cape support refer to Section 9.0.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
Figure 21 is the high level block diagram of the power section of the board.
This section describes the power section of the design and all the functions performed by the
TPS65217C.
The main Power Management IC (PMIC) in the system is the TPS65217C which is a single chip power management IC consisting of a linear dual-input power path, three step-down converters, and four LDOs. LDO stands for Low Drop Out. If you want to know more about an LDO, you can go to http://en.wikipedia.org/wiki/Low- dropout_regulator. If you want to learn more about step-down converters, you can go to http://en.wikipedia.org/wiki/DC-to-DC_converter
The system is supplied by a USB port or DC adapter. Three high-efficiency 2.25MHz step-down converters are targeted at providing the core voltage, MPU, and memory voltage for the board.
The step-down converters enter a low power mode at light load for maximum efficiency across the widest possible range of load currents. For low-noise applications the devices can be forced into fixed frequency PWM using the I2C interface. The step-down converters allow the use of small inductors and capacitors to achieve a small footprint solution size.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
Figure 22 is the high level block diagram of the TPS65217C.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
The board can also be powered from the USB port. A typical USB port is limited to 500mA max. When powering from the USB port, the VDD_5V rail is not provided to the expansion headers, so capes that require the 5V rail to supply the cape direct, bypassing the TPS65217C, will not have that rail available for use. The 5VDC supply from the USB port is provided on the SYS_5V, the one that comes from the TPS65217C, rail of the expansion header for use by a cape. Figure 24 is the connection of the USB power input on the PMIC.
U2
The selection of either the 5VDC or the USB as the power source is handled internally to the TPS65217C and automatically switches to 5VDC power if both are connected. SW can change the power configuration via the I2C interface from the processor. In addition, the SW can read the TPS65217C and determine if the board is running on the 5VDC input or the USB input. This can be beneficial to know the capability of the board to supply current for things like operating frequency and expansion cards.
It is possible to power the board from the USB input and then connect the DC power supply. The board will switch over automatically to the DC input.
A power button is connected to the input of the TPS65217C. This is a momentary switch, the same type of switch used for reset and boot selection on the board.
If you push the button the TPS65217C will send an interrupt to the processor. It is up to the processor to then pull the PMIC_POWER_EN pin low at the correct time to power
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
The power consumption of the board varies based on power scenarios and the board boot processes. Measurements were taken with the board in the following configuration:
-
DC powered and USB powered
-
HDMI monitor connected
-
USB HUB
-
4GB Thumbdrive
-
Ethernet connected @ 100M
-
Serial debug cable connected
Table 4 is an analysis of the power consumption of the board in these various scenarios.
MODE | USB | _ DC _ | DC+USB |
---|---|---|---|
|
TBD _ |
TBD _ |
TBD _ |
|
210 _ |
210 _ |
210 _ |
|
460 _ |
460 _ |
460 _ |
|
350 _ |
350 _ |
350 _ |
|
280 _ |
280 _ |
280 _ |
|
430 _ |
430 _ |
430 _ |
The current will fluctuate as various activates occur, such as the LEDs on and microSD/eMMC accesses.
The processor interacts with the TPS65217C via several different signals. Each of these signals is described below.
-
*I2C0*
I2C0 is the control interface between the processor and the TPS65217C. It allows the processor to control the registers inside the TPS65217C for such things as voltage scaling and switching of the input rails.
-
*PMC_POWR_EN*
On power up the VDD_RTC rail activates first. After the RTC circuitry in the processor has activated it instructs the TPS65217C to initiate a full power up cycle by activating the PMIC_POWR_EN signal by taking it HI. When powering down, the processor can take this pin low to start the power down process.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
Figure 25 shows the connections of each of the rails from the TPS65217C.
-
*VRTC Rail*
The VRTC rail is a 1.8V rail that is the first rail to come up in the power sequencing. It provides power to the RTC domain on the processor and the I/O rail of the TPS65217C. It can deliver up to 250mA maximum.
-
*VDD_3V3A Rail*
The VDD_3V3A rail is supplied by the TPS65217C and provides the 3.3V for the processor rails and can provide up to 400mA.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
-
*Power Sequencing*
The power up process is consists of several stages and events. Figure 26 describes the events that make up the power up process for the processer from the PMIC. This diagram is used elsewhere to convey additional information. I saw no need to bust it up into smaller diagrams. It is from the processor datasheet supplied by Texas Instruments.
Figure 27 the voltage rail sequencing for the TPS65217C as it powers up and the voltages on each rail. The power sequencing starts at 15 and then goes to one. That is the way the TPS65217C is configured. You can refer to the TPS65217C datasheet for more information.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
up, the RTC_PORZn pin, driven by the LDO_PGOOD signal from the TPS65217C, of the processor is released.
Once the RTC_PORZn reset is released, the processor starts the initialization process. After the RTC stabilizes, the processor launches the rest of the power up process by activating the PMIC_POWER_EN signal that is connected to the TPS65217C which starts the TPS65217C power up process.
The LDO_PGOOD signal is provided by the TPS65217C to the processor. As this signal is 1.8V from the TPS65217C by virtue of the TPS65217C VIO rail being set to 1.8V, and the RTC_PORZ signal on the processor is 3.3V, a voltage level shifter, U4, is used. Once the LDOs and switchers are up on the TPS65217C, this signal goes active releasing the processor. The LDOs on the TPS65217C are used to power the VRTC rail on the processor.
Figure 28 above shows two interfaces between the processor and the TPS65217C used for control after the power up sequence has completed.
The first is the I2C0 bus. This allows the processor to turn on and off rails and to set the voltage levels of each regulator to supports such things as voltage scaling.
The second is the interrupt signal. This allows the TPS65217C to alert the processor when there is an event, such as when the power button is pressed. The interrupt is an open drain output which makes it easy to interface to 3.3V of the processor.
This section covers three general power down modes that are available. These modes are only described from a Hardware perspective as it relates to the HW design.
-
*RTC Only*
In this mode all rails are turned off except the VDD_RTC. The processor will need to turn off all the rails to enter this mode. The VDD_RTC staying on will keep the RTC active and provide for the wakeup interfaces to be active to respond to a wake up event.
-
*RTC Plus DDR*
In this mode all rails are turned off except the VDD_RTC and the VDDS_DDR, which powers the DDR3L memory. The processor will need to turn off all the rails to enter this mode. The VDD_RTC staying on will keep the RTC active and provide for the wakeup interfaces to be active to respond to a wake up event.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
DDR3L Memory
The BeagleBone Black uses a single MT41K256M16HA-125 512MB DDR3L device from Micron that interfaces to the processor over 16 data lines, 16 address lines, and 14 control lines. On rev C we added the Kingston KE4CN2H5A-A58 device as a source for the DDR3L device.
The following sections provide more details on the design.
The design supports the standard DDR3 and DDR3L x16 devices and is built using the DDR3L. A single x16 device is used on the board and there is no support for two x8 devices. The DDR3 devices work at 1.5V and the DDR3L devices can work down to 1.35V to achieve lower power. The DDR3L comes in a 96-BALL FBGA package with
0.8 mil pitch. Other standard DDR3 devices can also be supported, but the DDR3L is the lower power device and was chosen for its ability to work at 1.5V or 1.35V. The standard frequency that the DDR3L is run at on the board is 400MHZ.
Figure 32 is the schematic for the DDR3L memory device. Each of the groups of signals is described in the following lines.
Address Lines: Provide the row address for ACTIVATE commands, and the column address and auto pre-charge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop).
Bank Address Lines: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA.
CK and CK# Lines: are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
Clock Enable Line: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE
*Reference Manual *
LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active power-down (row active in any bank). CKE is synchronous for power- down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power- down. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA.
DGND VDDS_DDR
3 DDR_RESETn
3
R97
R96
10K,1%
1.5K,1%
U12
T2
RESET#
J7
N3 _DDR_A0 _
DDR_A[15..0] 3
DDR_CLK
3 DDR_CLKn
3
K7 CK
K9 CKn
A0 P7
A1 P3
_DDR_A1 _
_DDR_A2 _
DDR_CKE
3
L2 CKE
A2 N2
_DDR_A3 _
DDR_CSn
3 DDR_RASn
3 DDR_CASn
3 DDR_WEn 3 DDR_D[15..0]
3 DDR_DQS1
3 DDR_DQSN1
3 DDR_DQS0
3 DDR_DQSN0
J3 K3 L3
DDR_D0 E3
DDR_D1 F7
DDR_D2 F2
DDR_D3 F8
DDR_D4 H3
DDR_D5 H8
DDR_D6 G2
DDR_D7 H7
DDR_D8 D7
DDR_D9 C3
DDR_D10 C8
DDR_D11 C2
DDR_D12 A7
DDR_D13 A2
DDR_D14 B8
DDR_D15 A3
C7 B7
F3 G3
CSn RASn CASn
WEn
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
UDQS UDQSn
LDQS LDQSn
A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BA0 BA1 BA2
ODT
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8
P8 _DDR_A4 _
P2 _DDR_A5 _
R8 _DDR_A6 _
R2 _DDR_A7 _
T8 _DDR_A8 _
R3 _DDR_A9 _
L7 _DDR_A10 _
R7 _DDR_A11 _
N7 _DDR_A12 _
T3 _DDR_A13 _
T7 _DDR_A14 _
M7 _DDR_A15 _
M2 _DDR_BA0 _
N8 _DDR_BA1 _
M3 _DDR_BA2 _
K1 _DDR_ODT _
B2 VDDS_DDR
R9 K2 K8 N1 N9 R1 D9
DDR_ODT 3
DDR_BA[2..0] 3
3 DDR_DQM1
3 DDR_DQM0
D3 E7
VDDS_DDR A1
C1 C9 D2 E9 F1 H2 H9
J1 J9 L1 L9
DDR_VREF
UDM LDM
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ7 VDDQ8 VDDQ9 VDDQ10
NC1 NC2 NC3 NC4
VDD9
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12
VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6
A9 B3
E1 G8 J2 J8 M1 M9 P1 P9 T1 T9
B1 B9 D1 D8 E2 E8 F9
DGND
VDDS_DDR R98
10K,1%
R100 10K,1%
C124
M8
VREF_CA
H1
VREF_DQ
VSSQ7
VSSQ8 VSSQ9
ZQ
G1 G9
L8 _ZQ R99 _
240E
C123
0.001uf ,50V
0.1uf ,6.3V
MT41K256M16HA -125:E
4Gb(512MB) DDR3L
DGND
DGND
DGND
Chip Select Line: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
The eMMC is a communication and mass data storage device that includes a Multi- MediaCard (MMC) interface, a NAND Flash component, and a controller on an advanced 11-signal bus, which is compliant with the MMC system specification. The nonvolatile eMMC draws no power to maintain stored data, delivers high performance across a wide range of operating temperatures, and resists shock and vibration disruption.
One of the issues faced with SD cards is that across the different brands and even within the same brand, performance can vary. Cards use different controllers and different memories, all of which can have bad locations that the controller handles. But the controllers may be optimized for reads or writes. You never know what you will be getting. This can lead to varying rates of performance. The eMMC card is a known controller and when coupled with the 8bit mode, 8 bits of data instead of 4, you get double the performance which should result in quicker boot times.
The following sections describe the design and device that is used on the board to implement this interface.
The device used is one of two different devices:
-
Micron MTFC4GLDEA 0M WT
-
Kingston KE4CN2H5A-A58
The package is a 153 ball WFBGA device on both devices.
*Reference Manual *
Figure 34 is the design of the eMMC circuitry. The eMMC device is connected to the MMC1 port on the processor. MMC0 is still used for the microSD card as is currently done on the original BeagleBone. The size of the eMMC supplied is now 4GB.
The device runs at 3.3V both internally and the external I/O rails. The VCCI is an internal voltage rail to the device. The manufacturer recommends that a 1uF capacitor be attached to this rail, but a 2.2uF was chosen to provide a little margin.
Pullup resistors are used to increase the rise time on the signals to compensate for any capacitance on the board.
VDD_3V3B
VDD_3V3B
U5A
U7
U13
A3
AM3358_ZCZ
T13
R162
0,1%,DNI
MEM_MNAND_2GB
The pins used by the eMMC1 in the boot mode are listed below in Table 6.
For eMMC devices the ROM will only support raw mode. The ROM Code reads out raw sectors from image or the booting file within the file system and boots from it. In raw mode the booting image can be located at one of the four consecutive locations in the main area: offset 0x0 / 0x20000 (128 KB) / 0x40000 (256 KB) / 0x60000 (384 KB). For this reason, a booting image shall not exceed 128KB in size. However it is possible to
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
LED | _ GPIO SIGNAL _ | PROC PIN |
---|---|---|
|
|
V15 _ |
|
|
U15 _ |
|
|
T15 _ |
|
|
V16 _ |
A logic level of “1” will cause the LEDs to turn on.
The design supports two groups of boot options on the board. The user can switch between these modes via the Boot button. The primary boot source is the onboard eMMC device. By holding the Boot button, the user can force the board to boot from the microSD slot. This enables the eMMC to be overwritten when needed or to just boot an alternate image. The following sections describe how the boot configuration works.
In most applications, including those that use the provided demo distributions available from beagleboard.org, the processor-external boot code is composed of two stages. After the primary boot code in the processor ROM passes control, a secondary stage (secondary program loader — "SPL" or "MLO") takes over. The SPL stage initializes only the required devices to continue the boot process, and then control is transferred to the third stage "U-boot". Based on the settings of the boot pins, the ROM knows where to go and get the SPL and UBoot code. In the case of the BeagleBone Black, that is either eMMC or microSD based on the position of the boot switch.
Figure 38 shows the circuitry that is involved in the boot configuration process. On power up, these pins are read by the processor to determine the boot order. S2 is used to change the level of one bit from HI to LO which changes the boot order.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
The first row in Figure 39 is the default setting. On boot, the processor will look for the eMMC on the MMC1 port first, followed by the microSD slot on MMC0, USB0 and UART0. In the event there is no microSD card and the eMMC is empty, UART0 or USB0 could be used as the board source.
If you have a microSD card from which you need to boot from, hold the boot button down. On boot, the processor will look for the SPIO0 port first, then microSD on the MMC0 port, followed by USB0 and UART0. In the event there is no microSD card and the eMMC is empty, USB0 or UART0 could be used as the board source.
The BeagleBone Black is equipped with a 10/100 Ethernet interface. It uses the same PHY as is used on the original BeagleBone. The design is described in the following sections.
Figure 40 shows the connections between the processor and the PHY. The interface is in the MII mode of operation.
VDD_3V3B
QFN32_5X5MM_EP3P3MM
This is the same interface as is used on the BeagleBone. No changes were made in this design for the board.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
-
*PHY_VDDCR Rail*
The PHY_VDDCR rail originates inside the LAN8710A. Filter and bypass capacitors are used to filter the rail. Only circuitry inside the LAN8710A uses this rail.
-
*SYS_RESET*
The reset of the LAN8710A is controlled via the SYS_RESETn signal, the main board reset line.
-
*Clock Signals*
A crystal is used to create the clock for the LAN8710A. The processor uses the RMII_RXCLK signal to provide the clocking for the data between the processor and the LAN8710A.
There are mode pins on the LAN8710A that sets the operational mode for the PHY when coming out of reset. These signals are also used to communicate between the processor and the LAN8710A. As a result, these signals can be driven by the processor which can cause the PHY not to be initialized correctly. To ensure that this does not happen, three low value pull up resistors are used. Figure 43 below shows the three mode pin resistors.
VDD_3V3B
This will set the mode to be 111, which enables all modes and enables auto-negotiation.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
The TDA19988 is a High-Definition Multimedia Interface (HDMI) 1.4a transmitter. It is backward compatible with DVI 1.0 and can be connected to any DVI 1.0 or HDMI sink. The HDCP mode is not used in the design. The non-HDCP version of the device is used in the BeagleBone Black design.
This device provides additional embedded features like CEC (Consumer Electronic Control). CEC is a single bidirectional bus that transmits CEC over the home appliance network connected through this bus. This eliminates the need of any additional device to handle this feature. While this feature is supported in this device, as of this point, the SW to support this feature has not been implemented and is not a feature that is considered critical. It can be switched to very low power Standby or Sleep modes to save power when HDMI is not used. TDA19988 embeds I2C-bus master interface for DDC-bus communication to read EDID. This device can be controlled or configured via I2C-bus interface.
The Figure 44 shows the connections between the processor and the HDMI framer device. There are 16 bits of display data, 5-6-5 that is used to drive the framer. The reason for 16 bits is that allows for compatibility with display and LCD capes already available on the original BeagleBone. The unused bits on the TDA19988 are tied low. In addition to the data signals are the VSYNC, HSYNC, DE, and PCLK signals that round out the video interface from the processor.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
There is a HDMI_INT signal that connects from the TDA19988 to the processor. This signal can be used to alert the processor in a state change on the HDMI interface.
There is an I2S audio interface between the processor and the TDA19988. Stereo audio can be transported over the HDMI interface to an audio equipped display. In order to create the required clock frequencies, and external 24.576MHz oscillator, Y4, is used. From this clock, the processor generates the required clock frequencies for the TDA19988.
There are three signals used to pass data from the processor to the TDA19988. SCLK is the serial clock. SPI1_CS0 is the data pin to the TDA199888. SPI1_D0 is the word sync pin. These signals are configured as I2S interfaces.
Audio is limited to CEA supported resolutions. LCD panels only activate the audio in CEA modes. This is a function of the specification and is not something that can be fixed on the board via a hardware change or a software change.
In order to create the correct clock frequencies, we had to add an external 24.576MHZ oscillator. Unfortunately this had to be input into the processor using the pin previously used for GPIO3_21. In order to keep GPIO3_21 functionality, we provided a way to disable the oscillator if the need was there to use the pin on the expansion header. Figure 45 shows the oscillator circuitry.
*Reference Manual *
Figure 46 shows the power connections to the TDA19988 device. All voltage rails for the device are at 1.8V. A filter is provided to minimize any noise from the 1.8V rail getting back into the device.
U11
HDMI_1V8
TDA19988
DGND
All of the interfaces between the processor and the TDA19988 are 3.3V tolerant allowing for direct connection.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
The PRU-ICSS module is located inside the AM3358 processor. Access to these pins is provided by the expansion headers and is multiplexed with other functions on the board. Access is not provided to all of the available pins.
All documentation is located at http://github.com/beagleboard/am335x_pru_package. This feature is not supported by Texas Instruments.
The features of the PRU-ICSS include:
Two independent programmable real-time (PRU) cores:
-
32-Bit Load/Store RISC architecture
-
8K Byte instruction RAM (2K instructions) per core
-
8K Bytes data RAM per core
-
12K Bytes shared RAM
-
Operating frequency of 200 MHz
-
PRU operation is little endian similar to ARM processor
-
All memories within PRU-ICSS support parity
-
Includes Interrupt Controller for system event handling
-
Fast I/O interface
Figure 49 is a high level block diagram of the PRU-ICSS.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
This section describes each of the connectors on the board.
The expansion interface on the board is comprised of two 46 pin connectors. All signals on the expansion headers are 3.3V unless otherwise indicated.
NOTE: Do not connect 5V logic level signals to these pins or the board will be damaged.
NOTE: DO NOT APPLY VOLTAGE TO ANY I/O PIN WHEN POWER IS NOT SUPPLIED TO THE BOARD. IT WILL DAMAGE THE PROCESSOR AND VOID THE WARRANTY.
NO PINS ARE TO BE DRIVEN UNTIL AFTER THE SYS_RESET LINE GOES HIGH.
Figure 50 shows the location of the expansion connectors.
The location and spacing of the expansion headers are the same as on the original BeagleBone.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
Table 13 lists the signals on connector P9. Other signals can be connected to this connector based on setting the pin mux on the processor, but this is the default settings on power up.
There are some signals that have not been listed here. Refer to the processor documentation for more information on these pins and detailed descriptions of all of the pins listed. In some cases there may not be enough signals to complete a group of signals that may be required to implement a total interface.
The PROC column is the pin number on the processor.
The PIN column is the pin number on the expansion header.
The MODE columns are the mode setting for each pin. Setting each mode to align with the mode column will give that function on that pin.
NOTES:
In the table are the following notations:
PWR_BUT is a 5V level as pulled up internally by the TPS65217C. It is activated by pulling the signal to GND.
# Both of these signals connect to pin 41 of P11. Resistors are installed that allow for the GPIO3_20 connection to be removed by removing R221. The intent is to allow the SW to use either of these signals, one or the other, on pin 41. SW should set the unused pin in input mode when using the other pin. This allowed us to get an extra signal out to the expansion header.
@ Both of these signals connect to pin 42 of P11. Resistors are installed that allow for the GPIO3_18 connection to be removed by removing R202. The intent is to allow the SW to use either of these signals, on pin 42. SW should set the unused pin in input mode when using the other pin. This allowed us to get an extra signal out to the expansion header.
NOTE: DO NOT APPLY VOLTAGE TO ANY I/O PIN WHEN POWER IS NOT SUPPLIED TO THE BOARD. IT WILL DAMAGE THE PROCESSOR AND VOID THE WARRANTY.
NO PINS ARE TO BE DRIVEN UNTIL AFTER THE SYS_RESET LINE GOES HIGH.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
PIN | PROC |
---|---|
|
|
|
|
|
|
|
|
|
1,2 _ |
GND _ |
3,4 _ |
|
5,6 _ |
|
7,8 _ |
|
9 |
|
10 |
A10 _ |
|
11 |
T17 _ |
|
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|
gpmc_csn4 |
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12 |
U18 _ |
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gpmc_csn6 |
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13 |
U17 _ |
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gpmc_csn5 |
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14 |
U14 _ |
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15 |
R13 _ |
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ehrpwm1_tripzone_input |
|
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16 |
T14 _ |
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17 |
A16 _ |
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18 |
B16 _ |
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19 |
D17 _ |
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20 |
D18 _ |
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21 |
B17 _ |
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22 |
A17 _ |
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23 |
V14 _ |
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rgmii2_rxdv |
|
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24 |
D15 _ |
|
|
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|
pr1_pru0_pru_r31_16 |
|
25 |
A14 _ |
|
|
|
mcasp0_axr3 |
|
|
|
pr1_pru0_pru_r31_7 |
|
26 |
D16 _ |
|
|
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|
|
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|
pr1_pru1_pru_r31_16 |
|
27 |
C13 _ |
|
|
|
mcasp0_axr3 |
|
|
|
pr1_pru0_pru_r31_5 |
|
28 |
C12 _ |
|
|
|
mcasp0_axr2 |
|
|
|
pr1_pru0_pru_r31_3 |
|
29 |
B13 _ |
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pr1_pru0_pru_r31_1 |
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30 |
D12 _ |
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pr1_pru0_pru_r31_2 |
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31 |
A13 _ |
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pr1_pru0_pru_r31_0 |
|
32 |
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33 |
C8 |
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34 |
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35 |
A8 |
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36 |
B8 |
|
37 |
B7 |
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38 |
A7 |
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39 |
B6 |
|
40 |
C7 |
|
41# _ |
D14 _ |
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D13 _ |
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pr1_pru0_pru_r31_6 |
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42@ _ |
C18 _ |
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B12 _ |
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Mcaspo_axr2 |
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pr1_pru0_pru_r31_4 |
|
|
GND _ |
** GPIO3_21 is also the 24.576MHZ clock input to the processor to enable HDMI audio. To use this pin the oscillator must be disabled.*
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
The USB Client connector is accessible on the bottom side of the board under the row of four LEDs as shown in Figure 52. It uses a 5 pin miniUSB cable, the same as is used on the original BeagleBone. The cable is provided with the board. The cable can also be used to power the board.
This port is a USB Client only interface and is intended for connection to a PC.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
Each board has a debug serial interface that can be accessed by using a special serial cable that is plugged into the serial header as shown in Figure 54 below.
Two signals are provided, TX and RX on this connector. The levels on these signals are 3.3V. In order to access these signals, a FTDI USB to Serial cable is recommended as shown in Figure 55 below.
Serial Debug Cable Pin 1
The cable can be purchased from several different places and must be the 3.3V version TTL-232R-3V3. Information on the cable itself can be found direct from FTDI at: http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL- 232R_CABLES.pdf
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
Access to the HDMI interface is through the HDMI connector that is located on the bottom side of the board as shown in Figure 57 below.
The connector is microHDMI connector. This was done due to the space limitations we had in finding a place to fit the connector. It requires a microHDMI to HDMI cable as shown in Figure 58 below. The cable can be purchased from several different sources.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
A place for an optional 20 pin CTI JTAG header is provided on the board to facilitate the SW development and debugging of the board by using various JTAG emulators. This header is not supplied standard on the board. To use this, a connector will need to be soldered onto the board.
If you need the JTAG connector you can solder it on yourself. No other components are needed. The connector is made by Samtec and the part number is FTR-110-03-G-D-06. You can purchase it from www.digikey.com.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
The main expansion headers are the same between the BeagleBone and BeagleBone Black. While the pins are the same, some of these pins are now used on the BeagleBone Black. The following sections discuss these pins.
The Power Expansion header was removed from the BeagleBone Black and is not available.
PAY VERY CLOSE ATTENTION TO THIS SECTION AND READ CAREFULLY!!
The LCD pins are used on the BeagleBone Black to drive the HDMI framer. These signals are listed in Table 15 below.
PIN | PROC | NAME | MODE0 |
---|---|---|---|
27 |
U5 |
|
|
28 |
V5 |
|
|
29 |
R5 |
|
|
30 |
R6 |
|
|
31 |
V4 |
|
|
32 |
T5 |
|
|
33 |
V3 |
|
|
34 |
U4 |
|
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35 |
V2 |
|
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36 |
U3 |
|
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37 |
U1 |
|
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38 |
U2 |
|
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39 |
T3 |
|
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40 |
T4 |
|
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41 |
T1 |
|
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42 |
T2 |
|
|
43 |
R3 |
|
|
44 |
R4 |
|
|
45 |
R1 |
|
|
46 |
R2 |
|
|
If you are using these pins for other functions, there are a few things to keep in mind:
-
On the HDMI Framer, these signals are all inputs so the framer will not be driving these pins.
-
The HDMI framer will add a load onto these pins.
-
There are small filter caps on these signals which could also change the operation of these pins if used for other functions.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
On power up, the eMMC is NOT reset. If you hold the Boot button down, this will force a boot from the microSD. This is not convenient when a cape is plugged into the board. There are two solutions to this issue:
-
Wipe the eMMC clean. This will cause the board to default to microSD boot. If you want to use the eMMC later, it can be reprogrammed.
-
You can also tie LCD_DATA2 low on the cape during boot. This will be the same as if you were holding the boot button. However, in order to prevent unforeseen issues, you need to gate this signal with RESET, when the data is sampled. After reset goes high, the signal should be removed from the pin.
BEFORE the SW reinitializes the pins, it MUST put the eMMC in reset. This is done by taking eMMC_RSTn (GPIO1_20) LOW *after* the eMMC has been put into a mode to enable the reset line. This pin does not connect to the expansion header and is accessible only on the board.
DO NOT automatically drive any conflicting pins until the SW enables it. This puts the SW in control to ensure that the eMMC is in reset before the signals are used from the cape. You can use a GPIO pin for this. No, we will not designate a pin for this function. It will be determined on a cape by cape basis by the designer of the respective cape.
Each cape must have its own EEPROM containing information that will allow the SW to identify the board and to configure the expansion headers pins as needed. The one exception is proto boards intended for prototyping. They may or may not have an EEPROM on them. An EEPROM is required for all capes sold in order for them operate correctly when plugged into the BeagleBone Black.
The address of the EEPROM will be set via either jumpers or a dipswitch on each expansion board. Figure 61 below is the design of the EEPROM circuit.
The EEPROM used is the same one as is used on the BeagleBone and the BeagleBone Black, a CAT24C256. The CAT24C256 is a 256 kb Serial CMOS EEPROM, internally organized as 32,768 words of 8 bits each. It features a 64−byte page write buffer and supports the Standard (100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocol.
*Reference Manual *
VDD_3V3
2,4,6
2,4,6
I2C2_SCL I2C2_SDA
SW1
SW1_A0 SW1_A1 SW1_A3
U18
6
5 SCL SDA
1
-
A0
-
A1 A2
8
VCC _
4
VSS _
7
WP
VDD_3V3
C130 0.1uF
DGND
DGND
SW DIP-2
CAT24C256W
The addressing of this device requires two bytes for the address which is not used on smaller size EEPROMs, which only require only one byte. Other compatible devices may be used as well. Make sure the device you select supports 16 bit addressing. The part package used is at the discretion of the cape designer.
In order for each cape to have a unique address, a board ID scheme is used that sets the address to be different depending on the setting of the dipswitch or jumpers on the capes. A two position dipswitch or jumpers is used to set the address pins of the EEPROM.
It is the responsibility of the user to set the proper address for each board and the position in the stack that the board occupies has nothing to do with which board gets first choice on the usage of the expansion bus signals. The process for making that determination and resolving conflicts is left up to the SW and, as of this moment in time, this method is a something of a mystery due to the new Device Tree methodology introduced in the 3.8 kernel.
Address line A2 is always tied high. This sets the allowable address range for the expansion cards to 0x54 to 0x57. All other I2C addresses can be used by the user in the design of their capes. But, these addresses must not be used other than for the board EEPROM information. This also allows for the inclusion of EEPROM devices on the cape if needed without interfering with this EEPROM. It requires that A2 be grounded on the EEPROM not used for cape identification.
*Reference Manual *
The EEPROMs on each expansion board are connected to I2C2 on connector P9 pins 19 and 20. For this reason I2C2 must always be left connected and should not be changed by SW to remove it from the expansion header pin mux settings. If this is done, the system will be unable to detect the capes.
The I2C signals require pullup resistors. Each board must have a 5.6K resistor on these signals. With four capes installed this will result in an effective resistance of 1.4K if all capes were installed and all the resistors used were exactly 5.6K. As more capes are added the resistance is reduced to overcome capacitance added to the signals. When no capes are installed the internal pullup resistors must be activated inside the processor to prevent I2C timeouts on the I2C bus.
The I2C2 bus may also be used by capes for other functions such as I/O expansion or other I2C compatible devices that do not share the same address as the cape EEPROM.
The design in Figure 62 has the write protect disabled. If the write protect is not enabled, this does expose the EEPROM to being corrupted if the I2C2 bus is used on the cape and the wrong address written to. It is recommended that a write protection function be implemented and a Test Point be added that when grounded, will allow the EEPROM to be written to. To enable write operation, Pin 7 of the EEPROM must be tied to ground. When not grounded, the pin is HI via pullup resistor R210 and therefore write protected. Whether or not Write Protect is provided is at the discretion of the cape designer.
*Variable & MAC Memory*
U7
VDD_3V3B
2,4
2,4
I2C0_SCL I2C0_SDA
6
5 SCL SDA
1
A0
A1 A2
8
VCC
VSS
7
WP
WP
R210 10K,1%
C102 0.1uf ,16V
DGND
DGND
CAT24C256W
256KX8
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
Table 18 is the locations in the EEPROM to set the I/O pin usage for the cape. It contains the value to be written to the Pad Control Registers. Details on this can be found in section 9.2.2 of the AM3358 Technical Reference Manual, The table is left blank as a convenience and can be printed out and used as a template for creating a custom setting for each cape. The 16 bit integers and all 16 bit fields are to be stored in Big Endian format.
Bit 15 PIN USAGE is an indicator and should be a 1 if the pin is used or 0 if it is unused.
Bits 14-7 RESERVED is not to be used and left as 0.
Bit 6 SLEW CONTROL 0=Fast 1=Slow
Bit 5 RX Enabled 0=Disabled 1=Enabled
Bit 4 PU/PD 0=Pulldown 1=Pullup.
Bit 3 PULLUP/DN 0=Pullup/pulldown enabled
1= Pullup/pulldown disabled
Bit 2-0 MUX MODE SELECT Mode 0-7. (refer to TRM)
Refer to the TRM for proper settings of the pin MUX mode based on the signal selection to be used.
The AIN0-6 pins do not have a pin mux setting, but they need to be set to indicate if each of the pins is used on the cape. Only bit 15 is used for the AIN signals.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
_ 15 _ | _ 14 _ | _ 13 _ | _ 12 _ | _ 11 _ | _ 10 _ | _ 9 _ | _ 8 _ | |||
---|---|---|---|---|---|---|---|---|---|---|
7 _ |
6 _ |
5 _ |
4 _ |
3 _ |
2 _ |
1 _ |
0 _ |
|
Conn |
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P9-23 |
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P9-14 |
EHRPWM1A |
||||||||
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P9-16 |
EHRPWM1B |
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P9-12 |
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P8-26 |
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P8-21 |
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P8-20 |
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P8-18 |
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P8-7 |
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P8-9 |
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P8-10 |
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P8-8 |
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P8-45 |
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P8-43 |
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P8-39 |
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P8-40 |
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P8-37 |
UART5_TXD |
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P8-38 |
UART5_RXD |
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P8-36 |
UART3_CTSN |
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P8-34 |
UART3_RTSN |
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P8-27 |
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P8-29 |
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P8-28 |
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P8-30 |
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P9-29 |
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P9-30 |
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P9-28 |
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P9-27 |
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P9-31 |
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P9-25 |
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||||||||
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
_ 15 _ | _ 14 _ | _ 13 _ | _ 12 _ | _ 11 _ | _ 10 _ | _ 9 _ | _ 8 _ | |||
---|---|---|---|---|---|---|---|---|---|---|
7 _ |
6 _ |
5 _ |
4 _ |
3 _ |
2 _ |
1 |
0 _ |
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0 _ |
0 _ |
0 _ |
0 _ |
0 _ |
0 _ |
0 _ |
0 _ |
0 _ |
0 _ |
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0 _ |
0 _ |
0 _ |
0 |
0 _ |
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REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
This section covers things to watch for when hooking up to certain pins on the expansion headers.
There are 16 pins that control the boot mode of the processor that are exposed on the expansion headers. Figure 63 below shows those signals as they appear on the BeagleBone Black.:
VDD_3V3A
DGND
If you plan to use any of these signals, then on power up, these pins should not be driven. If you do, it can affect the boot mode of the processor and could keep the processor from booting or working correctly.
If you are designing a cape that is intended to be used as a boot source, such as a NAND board, then you should drive the pins to reconfigure the boot mode, but only at reset. After the reset phase, the signals should not be driven to allow them to be used for the
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
It is allowed to only populate the pins you need. As this is a non-stacking configuration, there is no need for all headers to be populated. This can also reduce the overall cost of the cape. This decision is up to the cape designer.
For convenience listed in Table 19 are some possible choices for part numbers on this connector. They have varying pin lengths and some may be more suitable than others for your use. It should be noted, that the longer the pin and the further it is inserted into the BeagleBone Black connector, the harder it will be to remove due to the tension on 92 pins. This can be minimized by using shorter pins or removing those pins that are not used by your particular design. The first item in Table 18 is on the edge and may not be the best solution. Overhang is the amount of the pin that goes past the contact point of the connector on the BeagleBone Black
.
SUPPLIER | PARTNUMBER | TAIL LENGTH(in) | _ OVERHANG(in) _ |
---|---|---|---|
|
|||
|
|||
|
The G in the part number is a plating option. Other options may be used as well as long as the contact area is gold. Other possible sources are Sullins and Samtec for these connectors. You will need to ensure the depth into the connector is sufficient
For stacking configuration, the two 46 pin expansion headers use the same connectors. Figure 66 is a picture of the connector. These are dual row 23 position 2.54mm x 2.54mm connectors.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
Figure 68 is the connector configuration for stackable capes that does not provide all of the signals upwards for use by other boards. This is useful if there is an expectation that other boards could interfere with the operation of your board by exposing those signals for expansion. This configuration consists of a combination of the stacking and non- stacking style connectors.
The length of the pins on the expansion header has a direct relationship to the amount of force that is used to remove a cape from the BeagleBone Black. The longer the pins extend into the connector the harder it is to remove. There is no rule that says that if longer pins are used, that the connector pins have to extend all the way into the mating connector on the BeagleBone Black, but this is controlled by the user and therefore is hard to control. We have also found that if you use gold pins, while more expensive, it makes for a smoother finish which reduces the friction.
This section will attempt to describe the tradeoffs and things to consider when selecting a connector and its pin length.
Figure 69 shows the key measurements used in calculating how much the pin extends past the contact point on the connector, what we call overhang.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
DO NOT APPLY VOLTAGE TO ANY I/O PIN WHEN POWER IS NOT SUPPLIED TO THE BOARD. IT WILL DAMAGE THE PROCESSOR AND VOID THE WARRANTY.
NO PINS ARE TO BE DRIVEN UNTIL AFTER THE SYS_RESET LINE GOES HIGH.
This section describes the power rails for the capes and their usage.
The Table 1 describes the voltages from the main board that are available on the expansion connectors and their ratings. All voltages are supplied by connector P9. The current ratings listed are per pin.
Current | Name | _ P9 _ | Name | Current | _ GND _ | |
---|---|---|---|---|---|---|
1 |
_ 2 _ |
GND _ |
250mA |
|
||
3 |
_ 4 _ |
|
250mA |
1000mA |
|
|
5 |
_ 6 _ |
|
1000mA |
250mA |
|
|
7 |
_ 8 _ |
|
250mA |
|||
: |
_ : _ |
GND _ |
||||
43 |
44 |
GND _ |
GND _ |
The VDD_3V3B rail is supplied by the LDO on the BeagleBone Black and is the primary power rail for expansion boards. If the power requirement for the capes exceeds the current rating, then locally generated voltage rail can be used. It is recommended that this rail be used to power any buffers or level translators that may be used.
VDD_5V is the main power supply from the DC input jack. This voltage is not present when the board is powered via USB. The amount of current supplied by this rail is dependent upon the amount of current available. Based on the board design, this rail is limited to 1A per pin from the main board.
The SYS_5V rail is the main rail for the regulators on the main board. When powered from a DC supply or USB, this rail will be 5V. The available current from this rail depends on the current available from the USB and DC external supplies.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *
A slot is provided for the Ethernet connector to stick up higher than the cape when mounted. This also acts as a key function to ensure that the cape is oriented correctly. Space is also provided to allow access to the user LEDs and reset button on the main board.
Some people have inquired as to the difference in the radius of the corners of the BeagleBone Black and why they are different. This is a result of having the BeagleBone fit into the Altoids style tin.
It is not required that the cape be exactly like the BeagleBone Black board in this respect.
Capes larger than the standard board size are also allowed. A good example would be an LCD panel. There is no practical limit to the sizes of these types of boards. The notch for the key is also not required, but it is up to the supplier of these boards to ensure that the BeagleBone Black is not plugged in incorrectly in such a manner that damage would be cause to the BeagleBone Black or any other capes that may be installed. Any such damage will be the responsibility of the supplier of such a cape to repair.
As with all capes, the EEPROM is required and compliance with the power requirements must be adhered to.
REF: BBONEBLK_SRM BeagleBone Black System Rev C.1
*Reference Manual *