merging some SSE instructions semantics and items for qt and gtk ui.g…

…raphics packages.

README.rst

@@ -1338,6 +1338,14 @@ Please see `LICENSE`_.
 Changelog
 =========
 
+- `v2.4.4`_
+
+  * add some SSE instruction semantics
+  * add ui.graphics qt package with block/func/xfunc items classes
+  * add initial ui.graphics gtk package
+  * move vltable in ui.views.blockView class
+  * fix various x86/64 decoding/formating/semantics
+
 - `v2.4.3`_
 
   * add ui.graphics packages (emptied)
@@ -1444,6 +1452,7 @@ Changelog
 .. _ply: http://www.dabeaz.com/ply/
 .. _zodb: http://www.zodb.org
 .. _LICENSE: https://github.com/bdcht/amoco/blob/release/LICENSE
+.. _v2.4.4: https://github.com/bdcht/amoco/releases/tag/v2.4.4
 .. _v2.4.3: https://github.com/bdcht/amoco/releases/tag/v2.4.3
 .. _v2.4.2: https://github.com/bdcht/amoco/releases/tag/v2.4.2
 .. _v2.4.1: https://github.com/bdcht/amoco/releases/tag/v2.4.1

amoco/arch/x64/formats.py

@@ -1,5 +1,6 @@
 # -*- coding: utf-8 -*-
 
+from amoco.cas.expressions import regtype
 from amoco.arch.core import Formatter
 
 def pfx(i):
@@ -18,7 +19,12 @@ def deref(op):
     d = '%+d'%op.a.disp if op.a.disp else ''
     s = {8:'byte ptr ',16:'word ptr ',32:'dword ptr ', 128:'xmmword ptr '}.get(op.size,'')
     s += '%s:'%op.a.seg  if op.a.seg is not '' else ''
-    s += '[%s%s]'%(op.a.base,d)
+    b = op.a.base
+    if op.a.base._is_reg and op.a.base.type==regtype.STACK:
+        base10 = True
+    else:
+        base10 = False
+    s += '[%s%s]'%(op.a.base,op.a.disp_to_string(base10))
     return s
 
 def opers(i):

amoco/arch/x86/asm.py

@@ -392,7 +392,10 @@ def i_MOVSB(i,fmap):
 def i_MOVSW(i,fmap):
   _movs_(i,fmap,2)
 def i_MOVSD(i,fmap):
-  _movs_(i,fmap,4)
+  if i.misc['opdsz']==128:
+    sse_MOVSD(i,fmap)
+  else:
+    _movs_(i,fmap,4)
 
 #------------------------------------------------------------------------------
 def i_IN(i,fmap):
@@ -1208,3 +1211,218 @@ def i_SYSEXIT(i,fmap):
   fmap[cs]  = top(16)
   fmap[ss]  = top(16)
 
+def i_PAND(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = fmap(i.operands[1])
+  x=fmap(op1)&op2
+  fmap[op1] = x
+
+def i_PANDN(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = fmap(i.operands[1])
+  x=fmap(~op1)&op2
+  fmap[op1] = x
+
+def i_POR(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = fmap(i.operands[1])
+  x=fmap(op1)|op2
+  fmap[op1] = x
+
+def i_PXOR(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = fmap(i.operands[1])
+  x=fmap(op1)^op2
+  fmap[op1] = x
+
+def i_MOVQ(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = fmap(i.operands[1])
+  fmap[op1] = op2.zeroextend(op1.size)
+
+def sse_MOVSD(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = i.operands[1]
+  if op1._is_mem:
+    src = fmap(op2[0:op1.size])
+  elif op2._is_mem:
+    src = fmap(op2).zeroextend(op1.size)
+  fmap[op1] = src
+
+def i_MOVDQU(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = i.operands[1]
+  fmap[op1] = fmap(op2)
+
+def i_MOVDQA(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = i.operands[1]
+  fmap[op1] = fmap(op2)
+
+def i_MOVUPS(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = i.operands[1]
+  fmap[op1] = fmap(op2)
+
+def i_MOVAPS(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = i.operands[1]
+  fmap[op1] = fmap(op2)
+
+def i_PADDB(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = i.operands[1]
+  assert op1.size==op2.size
+  for __i in range(0,op1.size,8):
+    src1 = fmap(op1[__i:__i+8])
+    src2 = fmap(op2[__i:__i+8])
+    fmap[op1[__i:__i+8]] = src1+src2
+
+def i_PSUBUSB(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = i.operands[1]
+  assert op1.size==op2.size
+  for __i in range(0,op1.size,8):
+    src1 = fmap(op1[__i:__i+8])
+    src2 = fmap(op2[__i:__i+8])
+    res = src1-src2
+    fmap[op1[__i:__i+8]] = tst(src1<src2,cst(0,op1.size),res)
+
+def i_PMAXUB(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = i.operands[1]
+  assert op1.size==op2.size
+  for __i in range(0,op1.size,8):
+    src1 = fmap(op1[__i:__i+8])
+    src2 = fmap(op2[__i:__i+8])
+    fmap[op1[__i:__i+8]] = tst(src1>src2,src1,src2)
+
+def i_PMINUB(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = i.operands[1]
+  assert op1.size==op2.size
+  for __i in range(0,op1.size,8):
+    src1 = fmap(op1[__i:__i+8])
+    src2 = fmap(op2[__i:__i+8])
+    fmap[op1[__i:__i+8]] = tst(src1<src2,src1,src2)
+
+def i_PUNPCKHBW(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = i.operands[1]
+  assert op1.size==op2.size
+  src1 = fmap(op1)
+  src2 = fmap(op2)
+  val1 = (src1[i:i+8] for i in range(0,op1.size,8))
+  val2 = (src2[i:i+8] for i in range(0,op2.size,8))
+  res  = [composer([v1,v2]) for (v1,v2) in zip(val1,val2)]
+  fmap[op1] = composer(res)[op1.size:2*op1.size]
+
+def i_PUNPCKLBW(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = i.operands[1]
+  assert op1.size==op2.size
+  src1 = fmap(op1)
+  src2 = fmap(op2)
+  val1 = (src1[i:i+8] for i in range(0,op1.size,8))
+  val2 = (src2[i:i+8] for i in range(0,op2.size,8))
+  res  = [composer([v1,v2]) for (v1,v2) in zip(val1,val2)]
+  fmap[op1] = composer(res)[0:op1.size]
+
+def i_PCMPEQB(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = i.operands[1]
+  assert op1.size==op2.size
+  src1 = fmap(op1)
+  src2 = fmap(op2)
+  val1 = (src1[i:i+8] for i in range(0,op1.size,8))
+  val2 = (src2[i:i+8] for i in range(0,op2.size,8))
+  res  = [tst(v1==v2,cst(0xff,8),cst(0,8)) for (v1,v2) in zip(val1,val2)]
+  fmap[op1] = composer(res)
+
+def i_PSRLQ(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = i.operands[1]
+  assert op1.size==op2.size
+  src1 = fmap(op1)
+  src2 = fmap(op2)
+  val1 = (src1[i:i+64] for i in range(0,op1.size,64))
+  res  = [v1>>src2.value for v1 in val1]
+  fmap[op1] = composer(res)
+
+def i_PSLLQ(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = i.operands[1]
+  assert op1.size==op2.size
+  src1 = fmap(op1)
+  src2 = fmap(op2)
+  val1 = (src1[i:i+64] for i in range(0,op1.size,64))
+  res  = [v1<<src2.value for v1 in val1]
+  fmap[op1] = composer(res)
+
+def i_PSHUFB(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = i.operands[1]
+  assert op1.size==op2.size
+  sz = 4 if op1.size==128 else 3
+  src = fmap(op1)
+  mask = fmap(op2)
+  for i in range(0,op1.size,8):
+    srcb = src[i:i+8]
+    maskb = mask[i:i+8]
+    indx = maskb[0:sz]
+    if indx._is_cst:
+      sta,sto = indx.value*8,indx.value*8+8
+      v = src[sta:sto]
+      src[i:i+8] = tst(maskb[7:8],cst(0,8),v)
+      src[sta:sto] = tst(maskb[7:8],v,srcb)
+    else:
+      src[i:i+8] = tst(maskb[7:8],cst(0,8),top(8))
+  fmap[op1] = src
+
+def i_PINSRW(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = i.operands[1]
+  op3 = i.operands[2]
+  if op2._is_reg: op2 = op2[0:16]
+  src1 = fmap(op1)
+  src2 = fmap(op2)
+  if op3._is_cst:
+      sta,sto = op3.value*16,op3.value*16+16
+      src1[sta:sto] = src2
+  else:
+      src1 = top(src1.size)
+  fmap[op1] = src1
+
+def i_PEXTRW(i,fmap):
+  fmap[eip] = fmap[eip]+i.length
+  op1 = i.operands[0]
+  op2 = i.operands[1]
+  op3 = i.operands[2]
+  src2 = fmap(op2)
+  if op3._is_cst:
+      sta,sto = op3.value*16,op3.value*16+16
+      v = src2[sta:sto]
+  else:
+      v = top(16)
+  fmap[op1] = v.zeroextend(op1.size)

amoco/arch/x86/env.py

@@ -24,6 +24,7 @@
 is_reg_pc(eip)
 is_reg_flags(eflags)
 is_reg_stack(esp)
+is_reg_stack(ebp)
 
 ax = slc(eax,0,16,'ax')
 bx = slc(ebx,0,16,'bx')

amoco/arch/x86/formats.py

@@ -1,5 +1,6 @@
 # -*- coding: utf-8 -*-
 
+from amoco.cas.expressions import regtype
 from amoco.arch.core import Formatter,Token
 
 def pfx(i):
@@ -15,10 +16,14 @@ def mnemo(i):
 
 def deref(op):
     assert op._is_mem
-    d = '%+d'%op.a.disp if op.a.disp else ''
     s = {8:'byte ptr ',16:'word ptr ', 64:'qword ptr ', 128:'xmmword ptr '}.get(op.size,'')
     s += '%s:'%op.a.seg  if (op.a.seg is not '')  else ''
-    s += '[%s%s]'%(op.a.base,d)
+    b = op.a.base
+    if op.a.base._is_reg and op.a.base.type==regtype.STACK:
+        base10=True
+    else:
+        base10=False
+    s += '[%s%s]'%(op.a.base,op.a.disp_tostring(base10))
     return s
 
 def opers(i):

amoco/cas/expressions.py

@@ -648,6 +648,7 @@ def __init__(self,refname,**kargs):
         self.size = kargs.get('size',None)
         self.sf = False
         self._reg__protect = False
+        self.type = regtype.OTHER
 
     def __str__(self):
         return '@%s'%self.ref
@@ -948,9 +949,16 @@ def __init__(self,base,seg='',disp=0):
         self.sf   = False
 
     def __str__(self):
-        d = '%+d'%self.disp if self.disp else ''
+        d = self.disp_tostring()
         return '%s(%s%s)'%(self.seg,self.base,d)
 
+    def disp_tostring(self,base10=True):
+        if self.disp==0: return ''
+        if base10: return '%+d'%self.disp
+        c = cst(self.disp,self.size)
+        c.sf=False
+        return '+%s'%str(c)
+
     def toks(self,**kargs):
         return [(render.Token.Address,str(self))]
 

amoco/code.py

@@ -21,8 +21,6 @@
 
 from amoco.ui.views import blockView, funcView, xfuncView
 
-from amoco.ui.render import Token,vltable
-
 #-------------------------------------------------------------------------------
 class block(object):
     """
@@ -112,28 +110,9 @@ def cut(self,address):
             # TODO: update misc annotations too
             return len(I)-pos
 
-    def __vltable(self):
-        T = vltable()
-        n = len(self.instr)
-        for i in self.instr:
-            ins2 = i.toks()
-            if isinstance(ins2,str): ins2 = [(Token.Literal,ins2)]
-            ins = [ (Token.Address,'{:<10}'.format(i.address)),
-                    (Token.Column,''),
-                    (Token.Literal,"'%s'"%(i.bytes.encode('hex'))),
-                    (Token.Column,'') ]
-            T.addrow(ins+ins2)
-        if conf.getboolean('block','bytecode'):
-            pad = conf.getint('block','padding') or 0
-            T.colsize[1] += pad
-        if conf.getboolean('block','header'):
-            T.header = ('# --- block %s ---' % self.name).ljust(T.width,'-')
-        if conf.getboolean('block','footer'):
-            T.footer = '-'*T.width
-        return T
-
     def __str__(self):
-        return str(self.__vltable())
+        T = self.view._vltable(formatter='Null')
+        return '\n'.join([r.show(raw=True,**T.rowparams) for r in T.rows])
 
     def __repr__(self):
         return '<%s object (name=%s) at 0x%08x>'%(self.__class__.__name__,self.name,id(self))
@@ -207,6 +186,7 @@ def makemap(self,withmap=None,widening=True):
             if withmap is not None:
                 tmap <<= withmap
             heads[t] = tmap
+        self.misc['heads'] = heads
         # lets walk the function's cfg, in rank priority order:
         while len(spool)>0:
             count += 1

amoco/config.py

@@ -26,6 +26,7 @@
 # ui section
 conf.add_section('ui')
 conf.set('ui', 'formatter', 'Null')
+conf.set('ui', 'graphics', 'term')
 
 # overwrite with config file:
 import os

amoco/main.py

@@ -430,6 +430,9 @@ def check_func(self,node):
         # so we can return now :
         if len(T)>0:
             logger.verbose('extending cfg of %s (new target found)'%f)
+            for t in T:
+                for k,v in f.misc['heads'].iteritems():
+                    if v(pc)==t.cst: t.parent = k
         else:
             logger.info('lbackward: function %s done'%f)
             f.map = m