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[Docker][CI][RISC-V] Build riscv-isa-sim (spike) in ci_riscv Docker image to enable RISC-V unit testing #12534
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i retriggered the PR due to i think a network issue, and just have one question here.
cc @alter-xp can you take a look at the compiler used here and see if it would also work for you (or whether there's one in Zephyr we should consider)?
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AOT_SPIKE_RUNNER = AOTTestRunner( |
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just curious--i think this shouldn't be necessary if we are using Project API. did you need to use the AOTTestRunner infra?
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AFAIK AOTTestRunner and the MicroTVM Project API are just two different approaches. The latter is more powerful (allows autotuning, profiling) but comes with some overheads (due to RPC communication) while the test runner is very minimalistic but good enough for effective unit testing.
I went the AOTTestRunner approach to run the existing AOT/CRT related test cases in a straightforward fashion. I am not sure if this was one of you goals? Feel free to propose which test should be run using spike instead.
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ah gotcha; it's probably fine to take that approach. I think we do want to migrate the unit tests to Project API at some point (the advantage is that it forces the set of information passed from compiler to runtime to be presented in Model Library Format, thereby ensuring that we don't need side-channeled information beyond that format). it might be easier to leave the tests as-is for now, but i'm wondering if you foresee any challenge with using Project API with SPIKE? cc @mehrdadh @mkatanbaf @gromero
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I very much encourage to use project API from the first place, unless if there's a blocker. Initially, AOTTestRunner was introduced because at that point we didn't have host driven AOT and multi model support in MLF artifact. We're gonna remove AOTTestRunner in near future and consolidate all testing to a single flow.
turns out the network issue was actually a forgotten step in adding the image, which i've now hopefully rectified. |
@areusch it is probably a fault on my side. Seems like the spike test runner is enabled for every docker image instead of only in ci_riscv. I will try to come up with a followup. |
I got in touch with @alter-xp a while ago regarding the multilib limitations in their toolchain but if i remember correctly I did not get a response. What we have to consider is that in the end we will have to support both baremetal (most likely 32-bit MCUs) and linux-driven (i.e. Allwinner D1 based on C906 chip) RISC-V targets. The baremetal targets will most likely just use the MicroTVM platforms (Zephyr, Arduino, Spike) while the larger chips should just follow the usual TVM (RPC-Server) flow similar to the Aarch64 targets such as Raspberry Pis. Having a single toolchain for both strategies is desirable to keep maintenance low, but not a requirement for now IMHO. |
for baremetal we have the other newlib toolchain. Its instruction support is the same as that of Linux tools.It may solve the compilation problem here.
I'm sorry I didn't fully understand your question at that time. you can try this tool Xuantie-900-gcc-elf-newlib-x86_64-V2.6.0-20220715.tar.gz
It should be a common practice in the industry to provide two sets of compilation tools for baremetal and Linux driven. |
@alter-xp @PhilippvK gotcha--it's fine to have two toolchains in ci_riscv if they have a defined purpose. could we document that purpose in the install scripts? |
@areusch Currently, there is only one Xuantie compiler in ci_riscv. I ignored the situation of baremetal before. I can add it in image. But It seems better to add it directly to this pr because this PR needs to use it. What do you @PhilippvK think? |
one piece of advice: we don't quite have the debug flow well-polished for the type of PR that both adds a dependency to a docker container and then tries to use that dependency. the issue is that you can't pull the docker image built by the CI. for that reason, I suggest to split adds/uses of a new dependency into two PRs (happy to accept the first without the second as long as we're reasonably confident in landing the second). |
Sorry for the delay, I was not at home for the past few days. I will update the PR later this week @alter-xp Thank your for providing the Xuantie-900-gcc-elf-newlib-x86_64-V2.6.0-20220715.tar.gz. It seems to support the relevant extensions for baseline TVM integration and it does make sense to have both the the Linux and Newlib toolchain from a similar codebase. However it have two questions (unrelated to this pr) after shortly trying it out by myself:
It would be great if you could help me out with that! |
hi @PhilippvK
To link a 32bit program with P extensions, you can try this command
Since the file size needs to be taken into account when releasing the package, there is no library for all instruction combinations. The latest version of GCC source code will be opened in about two weeks, which may be helpful to you. |
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Here is a short update:
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thanks @PhilippvK !
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@PhilippvK looks like the PR is missing a file
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removing approval til the missing file is in
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File is added now. Thanks for the hint. |
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thanks @PhilippvK !
mkdir build | ||
cd build | ||
../configure --prefix=$RISCV --with-isa=RV32IMAC | ||
make -j`nproc` |
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slight pref for nproc - 1, in case you're locally building.
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Oops, I forgot to fix this... sorry for that, we can change it in a later commit.
RISCV_GCC_RELEASE="1.12.1" | ||
RISCV_GCC_VERSION="2.4.0" | ||
RISCV_GCC_KERNEL_VERSION="5.10.4" | ||
RISCV_GCC_DATE="20220428" | ||
RISCV_GCC_ARCH="x86_64" | ||
RISCV_GCC_BASE="Xuantie-900-gcc-linux-${RISCV_GCC_KERNEL_VERSION}-glibc-${RISCV_GCC_ARCH}-V${RISCV_GCC_VERSION}-${RISCV_GCC_DATE}" | ||
RISCV_GCC_EXT="tar.gz" | ||
RISCV_GCC_URL="https://github.com/T-head-Semi/csi-nn2/releases/download/v${RISCV_GCC_RELEASE}/${RISCV_GCC_BASE}.${RISCV_GCC_EXT}" | ||
DOWNLOAD_PATH="/tmp/${RISCV_GCC_BASE}.tar.gz" |
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RISCV_GCC_VERSION="2.6.0"
RISCV_GCC_ID="1659325511536"
RISCV_GCC_KERNEL_VERSION="5.10.4"
RISCV_GCC_DATE="20220715"
RISCV_GCC_ARCH="x86_64"
RISCV_GCC_BASE="Xuantie-900-gcc-linux-${RISCV_GCC_KERNEL_VERSION}-glibc-${RISCV_GCC_ARCH}-V${RISCV_GCC_VERSION}-${RISCV_GCC_DATE}"
RISCV_GCC_EXT="tar.gz"
RISCV_GCC_URL="https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//${RISCV_GCC_ID}/${RISCV_GCC_BASE}.${RISCV_GCC_EXT}"
DOWNLOAD_PATH="/tmp/${RISCV_GCC_BASE}.tar.gz"
You can use this code to update the toolchain version here to make it consistent with the newlib version
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Great, this is what I was looking for!
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hi @PhilippvK
These changes don't have much effect on me. Regarding the installation script here, I am also planning to separate it recently. I'm very glad you did it.
I also intend to do this. Should we also do it in this PR? |
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I added it to this PR. Please check if the changes are okay or if I am missing something @alter-xp. |
…iles [Docker] [RISC-V] move gcc toolchain installation out of csi-nn2 script [Docker] [RISC-V] move qemu installation out of csi-nn2 script
…u_install_core.sh script
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@alter-xp done :) |
thanks @PhilippvK @alter-xp ! we'll work on moving to newly-built docker images so you can start using this. |
@alter-xp Is there any update on this? |
hi, @PhilippvK. because of some other factors, the open time of gcc source code is delayed. The latest timetable is before December. Once the code is ready, I will inform you here. |
…mage to enable RISC-V unit testing (apache#12534) * Remove CSI-NN from ci_cortexm docker image * [Docker] [RISC-V] Split up CSI-NN2 installation script into several files [Docker] [RISC-V] move gcc toolchain installation out of csi-nn2 script [Docker] [RISC-V] move qemu installation out of csi-nn2 script * use updated version of qemu * [Docker] [RISC-V] Install newlib (baremetal) gcc toolchain * [Docker] [RISC-V] Install spike simulator * [Docker] move initialization of timezone and DEBIAN_FRONTEND to ubuntu_install_core.sh script
hi, @PhilippvK the new gcc source code has been opened, you can find here. I hope this will help you. |
Context
See Discussion in https://discuss.tvm.apache.org/t/coordination-of-risc-v-integration-in-tvm/13133
Summary
Update
Dockerfile.ci_riscv
to download RISC-V toolchain and compile Spike simulator (including proxy kernel)pk
,pk64
) are build to supportrv32gc
as well asrv64gc
targetsIntroduce AotTestRunner to use spike in unit tests (currently
rv32gc
only)Enable spike based AoTTestRunner for AoT/CRT related test cases
Future work
I have a followup ready based on this PR, which enable usage of spike for MicroTVM deployment (ProjectAPI Server).
Questions
That toolchain (
Xuantie-900-gcc-linux
) is mainly targeting 64-bit devices capable of running Linux. While it could be used for 32-bit bare metal targets as well (using the-static
compile flag), it is missing relevant multilib arches, such asrv32gc+ilp32d
to be usable. Thus, I use Sifives GCC (which does currenlty not support the RVV1.0 extension)cc @Mousius @areusch @driazati @gigiblender