Back to pull request #2758

CI: Skip half of RISC-V, Xtensa and Simulator targets when a Complex PR is created / updated #7733

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Run time

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Job	Run time
Fetch-Source	1m 21s
Fetch-Source	1m 21s
msys2-Arch / Select-Builds	3s
msys2-Arch / Select-Builds	3s
Linux-Arch / Select-Builds	3s
Linux-Arch / Select-Builds	3s
macOS-Arch / Select-Builds	4s
macOS-Arch / Select-Builds	4s
msys2	0s
msys2	0s
Linux (arm-01)	1m 47s
Linux (arm-01)	1h 12m 4s
Linux (other)	1m 46s
Linux (other)	57m 35s
Linux (risc-v-01)	1m 44s
Linux (risc-v-01)	24m 42s
Linux (sim-01)	1m 52s
Linux (sim-01)	1h 33m 56s
Linux (xtensa-01)	1m 46s
Linux (xtensa-01)	1h 35m 22s
Linux (arm-02)	1m 47s
Linux (arm-02)	1h 25m 1s
Linux (risc-v-02)	1m 39s
Linux (risc-v-02)	58m 56s
Linux (sim-02)	1m 47s
Linux (sim-02)	29m 41s
Linux (xtensa-02)	1m 46s
Linux (xtensa-02)	1h 36m 53s
Linux (arm-03)	1m 48s
Linux (arm-03)	41m 44s
Linux (risc-v-03)	1m 47s
Linux (risc-v-03)	1h 4m 33s
Linux (arm-04)	1m 46s
Linux (arm-04)	45m 24s
Linux (risc-v-04)	1s
Linux (risc-v-04)	40m 15s
Linux (arm-05)	1s
Linux (arm-05)	58m 6s
Linux (risc-v-05)	1s
Linux (risc-v-05)	41m 46s
Linux (arm-06)	1s
Linux (arm-06)	1h 18m 52s
Linux (risc-v-06)	1s
Linux (risc-v-06)	49m 14s
Linux (arm-07)	1s
Linux (arm-07)	1h 31m 47s
macOS	0s
macOS	0s
	19h 10m 14s