add coverage comments

ansys · Feb 9, 2022 · 00c0cc7 · 00c0cc7
1 parent f66814c
commit 00c0cc7
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Showing 2 changed files with 10 additions and 13 deletions.
diff --git a/_unittest/test_12_PostProcessing.py b/_unittest/test_12_PostProcessing.py
@@ -30,14 +30,11 @@ class TestClass:
     def setup_class(self):
         # set a scratch directory and the environment / test data
         with Scratch(scratch_path) as self.local_scratch:
-            try:
-                example_project = os.path.join(local_path, "example_models", test_project_name + ".aedtz")
-                self.test_project = self.local_scratch.copyfile(example_project)
-                example_project2 = os.path.join(local_path, "example_models", test_field_name + ".aedtz")
-                self.test_project2 = self.local_scratch.copyfile(example_project2)
-                self.aedtapp = Hfss(self.test_project)
-            except:
-                pass
+            example_project = os.path.join(local_path, "example_models", test_project_name + ".aedtz")
+            self.test_project = self.local_scratch.copyfile(example_project)
+            example_project2 = os.path.join(local_path, "example_models", test_field_name + ".aedtz")
+            self.test_project2 = self.local_scratch.copyfile(example_project2)
+            self.aedtapp = Hfss(self.test_project)
 
     def teardown_class(self):
         self.aedtapp._desktop.ClearMessages("", "", 3)

diff --git a/pyaedt/hfss.py b/pyaedt/hfss.py
@@ -1522,7 +1522,7 @@ def create_circuit_port_between_objects(
             portname = self._get_unique_source_name(portname, "Port")
 
             return self._create_circuit_port(out, impedance, portname, renorm, deemb, renorm_impedance=renorm_impedance)
-        return False
+        return False  # pragma: no cover
 
     @aedt_exception_handler
     def create_lumped_port_between_objects(
@@ -1597,7 +1597,7 @@ def create_lumped_port_between_objects(
             else:
                 faces = self.modeler.get_object_faces(sheet_name)
                 return self._create_port_terminal(faces[0], endobject, portname, renorm=renorm, iswaveport=False)
-        return False
+        return False  # pragma: no cover
 
     @aedt_exception_handler
     def create_spiral_lumped_port(self, start_object, end_object, port_width=None):
@@ -1858,7 +1858,7 @@ def create_voltage_source_from_objects(self, startobj, endobject, axisdir=0, sou
             )
             sourcename = self._get_unique_source_name(sourcename, "Voltage")
             return self.create_source_excitation(sheet_name, point0, point1, sourcename, sourcetype="Voltage")
-        return False
+        return False  # pragma: no cover
 
     @aedt_exception_handler
     def create_current_source_from_objects(self, startobj, endobject, axisdir=0, sourcename=None, source_on_plane=True):
@@ -1915,7 +1915,7 @@ def create_current_source_from_objects(self, startobj, endobject, axisdir=0, sou
             )
             sourcename = self._get_unique_source_name(sourcename, "Current")
             return self.create_source_excitation(sheet_name, point0, point1, sourcename, sourcetype="Current")
-        return False
+        return False  # pragma: no cover
 
     @aedt_exception_handler
     def create_source_excitation(self, sheet_name, point1, point2, sourcename, sourcetype="Voltage"):
@@ -2038,7 +2038,7 @@ def create_wave_port_between_objects(
             else:
                 faces = self.modeler.get_object_faces(sheet_name)
                 return self._create_port_terminal(faces[0], endobject, portname, renorm=renorm, iswaveport=True)
-        return False
+        return False  # pragma: no cover
 
     @aedt_exception_handler
     def create_floquet_port(